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A microprocessor-based system has an 8-bit data bus and a 10-bit address bus. It requires a 16-bit output port having two consecutive addresses starting from an even address. Furthermore, address needs to be configurable to any even address between 0X00 and 0xFF.

Assume that the following MSI/LSI components are available in addition to basic logic gates.

  • An 8-bit binary magnitude comparator
  • Two 8-bit latches with active low clock input and an output enable input

Sketch a block diagram of the output port and briefly explain its operation.

If this question seems to be vague to you (it was to me), I cannot explain it further.

This is what I came up with for my solution to this problem. (I'm not sure whether I have used standard block diagram components/conventions) Solution

Diagram explanation:-

The light blue colour components are the latches and they are activated based on the clock signal The light teal colour component is the comparator that compares A0 bit of the address bus(extended with 0) with "00000000" (Because any even number will end with '0'). And well, lets just say that the "output enable input" has a typo in the original question and is a general input that acts as an enable input for the latch. (ie. new data can be written the latch is enabled and on a rising/falling edge of the clock) D6 is the control signal that tells whether the data bus is used to send an address.

pa1
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    In the "requirements specification", there is no value between `between` and `and`. Where does "the `D6` idea" come from? Where does `Clock` come from? What about *latches with … an output enable input*? – greybeard Jul 02 '23 at 16:23
  • @greybeard I added the missing value. The D6 idea is that when the data bus is used to send addresses through (D0 - D5), D6 will be used as a control signal to say whether its an address or data. That's what I thought... As for the last two questions you asked I'm not so sure. I assumed the microprocessor to have one clock – pa1 Jul 02 '23 at 16:34
  • `let's just say that the "output enable input" has a typo` Your question, your call. For this Q&A… – greybeard Jul 02 '23 at 17:31
  • You might consider designing the 8-bit case first, then expanding to 16-bits. From my reading of the question, the output enable issue is unspecified, and you could make it always-on. It's the latching and addressing you have to think about. – jonathanjo Jul 02 '23 at 18:13
  • Here some more clues: The question should probably have indicated there was some kind of `WR` signal -- all microprocessors have them. And somehow you have to clock your latches only whether the address is correct. Try thinking about how you can join the `A0-A9` together with the configuration bits (what would you choose for these?) and `WR` to generate your active low clock signals. – jonathanjo Jul 02 '23 at 20:36
  • What happened to D7 pin? In the diagram I can see the D0-D6 is used but there is no D7 – Sanjula Gathsara Jul 07 '23 at 04:13

1 Answers1

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Things I'd require from the block diagram:

  • Two 8-bit latches for the 16-bit output
  • A way to configure one of 128 even addresses between x00 and xFF
  • An 8-bit comparator comparing addresses
  • some signal from the microprocessor to indicate the value from the bus should be latched

– and an explanation of operation

There are tricky points (thinking full/bonus points/top grades):

  • How does whatever is reading the output port get to know about a newly set value?
  • with an 8-bit data bus and a 16-bit output port, a third 8-bit latch may be necessary to avoid putting out a value half old, half new.

any even number will end with "10" (rev. 5) has been plain wrong.
I think you misinterpret having two consecutive addresses starting from [a configurable] even address:
the port is addressed by all address bits but the LSB.
An 8-bit magnitude comparator will take care of eight bits: check one remaining address bit separately. It's simpler to check A₉ or(/and) A₈ as they need to be 0.

greybeard
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