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I am trying to simulate the LT8310 part in LTspice. Based on my understanding, this part can operate in either the current mode or the duty mode. I am interested in the current mode design. The block diagram of the part indicates that the VC (control pin) voltage level is set by the error amplifier between FBX and 1.6 V. There is an error amplifier between the amplified VSENSE voltage and the VC pin, which can reset the PWM control logic and adjust the duty cycle. Additionally, there is a parameter called RSET that needs to be modified since we are not using the duty cycle mode. This parameter sets the maximum duty cycle. BLK DIAGRAM In my design, the input voltage is 24 V, the output voltage is 20 V, and the maximum current is 6 A. The frequency has been chosen as 400 kHz due to the use of an external clock. I have performed careful calculations, but I am encountering a negative value for the RSENSE current. I have estimated a value of approximately 6000 pF for C_RST, but it results in a VSENSE greater than 125 mV. If I make it smaller, it solves this issue but still negative ISENSE current. I would appreciate it if someone could identify which parameter is causing this issue so that I can further investigate.

LTSPICE IRSENSE VSENSE UPDATED I have updated the post with the input I have received, but the issue in my simulation still persists. I have included the steps I have taken.

Step1,2,3

Step4,5,6

Step7,8,9

This is the updated simulation: Updated simulation

IRSENSE EMLARGED IRSENSE

Still, the same issue persists. Although I can understand the concepts of magnetizing inductance (self-inductance) and primary inductance (coupled inductance) in theory, I am uncertain if I have modeled them correctly in LTspice.

chami
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  • What kind of design steps did you perform and can disclose? For example of what I'd like to see, there's some examples [performed at this Analog website](https://www.analog.com/en/analog-dialogue/articles/modeling-and-control-for-current-mode-buck-converter-with-a-secondary-lc-filter.html). (I'm lazy. Sorry.) – periblepsis Jun 21 '23 at 00:43
  • You cannot have a 6-nF capacitor across a MOSFET switching at 400 kHz unless you would ensure zero-voltage switching (ZVS) across that transistor. It is not the case here and the drain will always end up at \$V_{in}\$ before the transistor is being turned on again so you can imagine the switching loss here. The negative current you see - I assume the spikes below ground in your sims - can come from various things like resonance, capacitor discharge (the 6-nF cap.) etc. – Verbal Kint Jun 21 '23 at 05:44
  • @periblepsis Thank you for your response. I followed all the formulas and calculations provided in the datasheet. However, I encountered uncertainty when trying to determine the value for the magnetizing inductance from the SRF1280-3R3Y datasheet. https://www.mouser.com/datasheet/2/54/SRF1280-1391377.pdf – chami Jun 21 '23 at 18:02
  • @periblepsis I have added the steps. I would greatly appreciate it if you could take a look and provide some advice. – chami Jun 26 '23 at 15:50

1 Answers1

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I think the issue is coming from the magnetizing inductance which is way too low in your simulation. This inductor \$L_m\$ does not participate to the energy transfer and forces the circulation of the magnetizing current. This current drives the transformer magnetic operating point and incurs core losses when too large. It has therefore to be minimized for best performance.

In this type of structure, the reset is done by letting the drain swing beyond the input voltage via a resonant waveform. However, this reset voltage will land to \$V_{in}\$ before the switch turns back on again, bringing turn-on losses. You then realize that this capacitor cannot be of too high a value otherwise switching losses will become unacceptable. Similarly, if too low, then the reset voltage on the drain may exceed the transistor \$BV_{dss}\$ and destroy it.

I would start backward and fix a certain amount of acceptable switching losses \$P_{sw}\$ based on the 400-kHz switching frequency and fix the maximum capacitance you can live with: \$C_{RST}<\frac{2P_{sw}}{F_{sw}V_{in}^2}\$. For instance, if I say 100 mW is the max you can accept, then the total capacitance (including the transistor \$C_{oss}\$) should be less than 868 pF. Then, from the reset voltage formula given by the data-sheet, you could extract the minimum acceptable magnetizing inductance for your transformer and design it to meet this number. In the below example, the minimum magnetizing inductance is 253 µH:

enter image description here

But you see how the voltage on the drain can swing so it is an iterative design process to keep all these operating parameters under control.

I gave a quick look with SIMPLIS using one my ready-made templates and it seems to work ok:

enter image description here

You can see that you have a negative magnetizing current which is indicating the transformer operates in quadrants I and III, allowing to push the duty ratio beyond 50%. I looked at these reset techniques for the forward converter, including active clamp, in chapter 8 of my book.

Verbal Kint
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  • I am thrilled that the author of the book I'm currently reading has answered my question, even though I'm still on Chapter 1. I diligently followed all the equations provided in the datasheet, but I encountered difficulty in finding the magnetizing inductance for the SRF1280-3R3Y transformer in the datasheet (https://www.mouser.com/datasheet/2/54/SRF1280-1391377.pdf). To address this, I approximated the magnetizing inductance as 3.3uH, assuming that the ideal scenario would be infinite inductance and the worst-case would be 3.3uH. – chami Jun 21 '23 at 17:53
  • However, I now understand that my assumption was incorrect. Could you please guide me on how to obtain the actual Lm value from the datasheet? – chami Jun 21 '23 at 17:53
  • In your schematic, it seems that including the magnetizing inductance (LM) is necessary. However, I noticed that Analog Devices' simulation of the LT8310 on their website (https://www.analog.com/en/products/lt8310.html#product-tools) does not include the magnetizing inductance. I have also attempted to fix the issue by changing the C_RST value to 250pF, but it did not resolve the problem. This has led me to wonder if I should learn how to model the magnetizing inductance in LTspice. – chami Jun 21 '23 at 17:55
  • Additionally, I examined your model, and it appears to be based on voltage feedback mode. Correct? – chami Jun 21 '23 at 17:56
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    Hello, what you've used are coupled inductors hence the naturally-low values. You should select a true transformer like you can find off-the-shelf from known suppliers. The magnetizing inductance plays a role because it sets the mag. current which resonates with the reset capacitor. There is no difference whether this is voltage- or current-mode control for the static control, the duty ratio \$D\$ will be similar between the two. – Verbal Kint Jun 21 '23 at 18:03
  • @ Verbal Knit Thank you. I will delve into Chapter 8 to gain a better understanding of the reset capacitor concept. Later, I will provide an update with a simulation that incorporates the effect of the magnetizing inductance. – chami Jun 21 '23 at 18:14
  • @ Verbal Knit I have updated the post. I would greatly appreciate it if you could provide some advice or guidance regarding my issue. – chami Jun 26 '23 at 15:49
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    I would recommend you simulate the power stage alone, as I did, with a square source driving the MOSFET. Once this part including the transformer is ok, then you can include the LT controller. For the transformer, I never use the coupled-inductor model but more a dc transformer to which you separately add a magnetizing inductor and a leakage term. Easier to visualize and you can probe the mag. current in a forward converter. – Verbal Kint Jun 26 '23 at 18:49