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Does pci require routing mechanism in those 2 cases

  1. The two devices are on the same PCI bus and aren't seperated by a bridge.

  2. They aren't on the same PCI bus.

I don't think it requires a routing mechanism in first case because pci devices all share the same pci bus. (correct me if I'm wrong)

John greg
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  • To be clear -- is this original (90s era parallel) PCI? What "routing mechanism" are you concerned with? Have you read (or access to) the standard? – Tim Williams Jun 05 '23 at 21:55
  • @TimWilliams yes the parallel bus pci. I did read specification for it but it doesn't mention anything about routing it just says all devices decode the address to see if they are the target of the transaction, hence I don't know if there exists types of routing in pci (note: I said pci and not pcie because I know pcie has routing based on id or address) so I would be thankfull if you could mention all routing mechanisms If any – John greg Jun 05 '23 at 22:00
  • I'm not an expert on PCI myself, but that should help clear things up for those that are. My vague understanding is, it's not routed, it's a one-to-any interface where any device granted bus master can transmit as it sees fit; and a bridge then would need to be programmed with a range of addresses to map. But someone more authoritative can fill in to be sure. – Tim Williams Jun 05 '23 at 22:05
  • @Johngreg Every 33 MHz PCI device can act as a bus master. Transfers are limited to bursts -- no "DMA" is permitted, though. Because of other limitations (the requirement for permitting two bridge ICs -- 2 loads -- there can be at most 4 socketed boards on each PCI. This is because 10 pF is allocated for the connector and another 10 pF is allocated for the board, so 20 pF per slot. With four sockets that's 80 pF. The remaining 20 pF is allocated to the 2 ICs that may also be present (1 for sure, obviously.) – periblepsis Jun 05 '23 at 22:40
  • @Johngreg I've not had to worry about this, so my memory may be wrong. But I seem to recall reading that for communication between devices on different bus segments, the intervening IC mediates and should respond as a slave to the master board and as a master to the slave board when the two are communicating through the bridging IC. The first PCI segment, memory serving, is on the southbridge IC. (That's also where the old ISA bus was at, back when ISA was still supported by the southbridge, though the handling of ISA DMA was always rather buggy.) – periblepsis Jun 05 '23 at 22:42
  • @periblepsis I thought pci bus masters could perform dma , could you explain why they can't – John greg Jun 05 '23 at 23:08
  • @Johngreg I meant it from the meaning taken from the ISA bus DMA transaction, which can be of unlimited/unspecified length. PCI doesn't support unlimited/unspecified transaction lengths. So the southbridge (when it supported ISA DMA) had to chop them up for PCI while sustaining them on ISA. It was a pain and a source of buggy southbridge chips. PCI supports transaction *bursts*. – periblepsis Jun 05 '23 at 23:27
  • Building on @periblepsis point, any bus master can perform burst accesses to memory space. That is effectively the same as general DMA. PCI memory space can contain memory (RAM, EPROM, ROM etc.), I/O registers or be unoccupied. – TonyM Jun 05 '23 at 23:58

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