Several upcoming or future CMOS process nodes are said to offer some kind of backside power delivery for Silicon CMOS transistors, so the precious area in the lower metal layers is freed up for signal interconnects increasing integration density. Source from imec.
Why does this even work from a signal integrity point-of-view?
I believe, most logic gates or memory cells use single-ended signalling. If you take away VDD and VSS traces from the neighborhood of the signal traces, then signal traces will use eachother as return current conductors at high frequency, summoning pure signal integrity desaster. This violates basically every rule for good layout.
One could remedy it by adding dedicated return current traces to the front side again, effectively creating differential signalling, but wouldn't that undermine the whole point of improving the integration density?
Please note, I am purely interested in the effect of backside power distribution on signal integrity. I am not interested in thermal or economic aspects of such a design.
