Bad default binding, component port not on entity

Question

I am trying to write a testbench for a basic component, but I am getting an error saying:

bad default binding for component instance (component port not on entity)

I have tried recompiling multiple times in both quartus and questa, have restarted both programs, and nothing seems to work. I have attached the code for the component and its testbench, and an image of the error message in questa. Any help is greatly appreciated.

Component:

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity H1_dataflow is
    Port(
        F3      : out   std_logic;
        F2      : out       std_logic;
        F1      : out       std_logic;
        F0      : out       std_logic;
        A       : in        std_logic;
        B       : in        std_logic;
        C       : in        std_logic;
        D       : in        std_logic
    );
end H1_dataflow;

architecture dataflow of H1_dataflow is

begin
    
    F3 <= (NOT(A) AND (NOT(B) OR NOT(D))) OR (NOT(B) AND C);
    F2 <= (NOT(A) AND B AND NOT(D)) OR (B AND NOT(C) AND D) OR (A AND C AND D) OR (A AND NOT(B) AND NOT(D));
    F1 <= (NOT(A) AND D) OR (A AND C AND NOT(D)) OR (A AND NOT(B) AND NOT(D)) OR (A AND NOT(B) AND C);
    F0 <= (NOT(A) AND NOT(C) AND NOT(D)) OR (A AND B AND C) OR (A AND C AND NOT(D)) OR (A AND NOT(B) AND NOT(C)) OR (NOT(A) AND NOT(B) AND C AND D);
        
end dataflow;

Testbench:

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;

entity H1_dataflow is

end H1_dataflow;

architecture test of H1_dataflow is

component H1_dataflow
    Port(
        F3      : out   std_logic;
        F2      : out       std_logic;
        F1      : out       std_logic;
        F0      : out       std_logic;
        A       : in        std_logic;
        B       : in        std_logic;
        C       : in        std_logic;
        D       : in        std_logic
    );
end component;

signal inputs               : std_logic_vector(3 downto 0);
signal test_output      : std_logic_vector(3 downto 0);
signal exp_output           : std_logic_vector(3 downto 0);

begin

    dev_to_test: H1_dataflow
    port map(
            F3 => test_output(3), F2 => test_output(2), F1 => test_output(1), F0 => test_output(0),
            A => inputs(3), B => inputs(2), C => inputs(1), D => inputs(0)
    );
    
    expected_proc : process(inputs)
    begin
        case inputs is
            when "0000" =>
                exp_output <= "1001";
            when "0001" =>
                exp_output <= "1010";
            when "0010" =>
                exp_output <= "1000";
            when "0011" =>
                exp_output <= "1011";
            when "0100" =>
                exp_output <= "1101";
            when "0101" =>
                exp_output <= "0110";
            when "0110" =>
                exp_output <= "1100";
            when "0111" =>
                exp_output <= "0010";
            when "1000" =>
                exp_output <= "0111";
            when "1001" =>
                exp_output <= "0001";
            when "1010" =>
                exp_output <= "1111";
            when "1011" =>
                exp_output <= "1110";
            when "1100" =>
                exp_output <= "0000";
            when "1101" =>
                exp_output <= "0100";
            when "1110" =>
                exp_output <= "0011";
            when "1111" =>
                exp_output <= "0101";
            when others => 
                exp_output <= (others => 'X');
        end case;
    end process expected_proc;
    
    stimulus : process
    variable ErrCnt : integer := 0;
    
    begin
        for i in 0 to 15 loop
            inputs <= std_logic_vector(to_unsigned(i,inputs'length));
            
            wait for 10 ns;
            
            if(exp_output /= test_output) then
                 ErrCnt := ErrCnt + 1;
         end if;
        end loop;
        
      if(ErrCnt = 0) then
          report "SUCCESS! Full Adder test completed.";
      else
          report "The Full Adder is broken." severity error;
      end if;
    end process stimulus;
end test;

Questa Error:

score 1 · Accepted Answer · answered May 31 '23 at 19:28

You declared 2 entities with the same name (H1_dataflow): one in your "Component" and one in your "Testbench".

One way to fix it is to rename the testbench entity. For example, change:

entity H1_dataflow is

end H1_dataflow;

architecture test of H1_dataflow is

to:

entity testbench is
end testbench; 

architecture test of testbench is

This EDA Playground link shows that the error you reported is fixed.

Bad default binding, component port not on entity

1 Answers1