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I have a really weird issue with the layout of my design (TSMC 0.18um BCD). I have three components (A, B and C), all of which are LVS and DRC clean and sitting in their own respectable NBLs. Component A has a large MIMcap (multiplier 60) with a 1.8V, 5 V, floating 5V and HV supplies, B is a logic block at 1.8 V, and component C has two separate 1.8 V supplies (AVDD and DVDD) and is covered by MIMcap as well. Now I am making a higher-level component D that includes A, B and C together.

My issue is that although components A, B and C are all DRC/LVS clean, after I instantiated A, B, C in component D, all of the MIMcaps of A become not recognised in the schematic. I could not initially find the issue so I did the following in the schematic and layout:

  1. Instantiated only A with all ports NC. Result: LVS clean

  2. Added supply pins to A. Result: LVS clean.

  3. Added all other pins apart from the ones that should come from B and C. Result: LVS clean.

  4. Include component B and connect to A. Result: MIMcap not recognised. >> I then pinpointed this to having VSS of A (5V NBL) connected to VSS of B (1V8 NBL). Really not sure why this is an issue...

  5. Create a separate ground pin for A and B. Result: LVS clean.

  6. At this point I have LVS clean and continue with the incremental approach: Instantiate C with all pins except substrate NC. Place it anywhere in the layout away from A and B + connect SUB through M1. Result: LVS not clean, MIMcaps not recognised in the schematic and all nodes related to these capacitors not recognised correctly either.

Does anyone know what could cause such an error when all components are LVS clean? Where could I find a clue about this? Does anyone have any ideas why having VSS connected (point 3) and adding a new component (point 4) results in the same error?

One thing to note here is that the MIMcap in A is a bootstrapped capacitor that generates a floating 5 V supply, but I do not see the direct link of it being the issue...

Any help is highly appreciated!

Nitrogen
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    What LVS tool are you using? PVS? Assura? Do you have an LVS report you can share for a case where the Mimcap is not recognized? Are the VSS subtrates (isolated by the NBLs) properly bonded to each other, and does schematic Check and Save show any issues? – nanofarad May 26 '23 at 20:28
  • Hi, I have been analysing the issue and found the possible culprit: I have a subcomponent of A that includes a MIMcap with a multiplier of 60. The LVS of this subcomponent is correct, but the LVS includes a list of "Ambiguity Resolution Points", all of which are these MIMcaps. Based on the information on the internet, if there are too many ambiguities, LVS errors can arise moving forward. I am not sure why it reports these devices as ambiguous, because both top and bottom plates of these MIMs are connected to nodes with ports on them. Of course, they become inner nodes in component A. – Nitrogen May 29 '23 at 15:44
  • I am using Calibre. – Nitrogen May 29 '23 at 16:18
  • The LVS decks often don't let you union non-mask LVS-marker layers -- that is to say, the devices have to be separate polygons of the LVS marking layers. So when you say "covered by MIMCAP" ... I question whether you have LVS layers abutting that should not be. It is often very hard to figure out the rules for LVS layers without using Pcell generators. But since you are clean in isolation, I'd guess it's because you're unioning marking layers. – stevesliva May 31 '23 at 03:32

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