PCB design for high-frequency differential lanes (PCIe and USB)

Question

I have designed an M2 adapter which converts from KeyE to KeyM.

Practically this means my board can be inserted into a KeyE slot, and it can host a KeyM SSD.

Gray rectangle is the KeyM socket on my board:

Design involves 10uF caps on 3.3V on both sides of the socket to have proper buffering for the NVMe SSD.

Design also breaks out USB (2.0) from the KeyE pins.

I tried to length-match the diffpairs as much as I can:

USB (97.2% : 100%):

PCIe RX (100% : 100%):

PCIe TX (100% : 100%):

PCIe Clk (100% : 99.2%):

Although I haven't done any impedance matching (yet) on this desing, I have a few concerns I need to address:

1. PCB stackup

As these wires are all differential coplanars (with a few vias):

I'm curious if I need to use 4-layer PCB or 2-layer is sufficient. Impedance matching can be done, as due to differential coplanar structure of diffpairs trace width and spacing is very well managable.

However, for traces on the bottom (especially PCIe RX): this board will be inserted into a motherboard. So for bottom traces there will be massive high-frequency signals underneath them on the motherboard within 1-2mm distance. Shall I take this into consideration and design a 4-layer stackup, or motherboards are usually don't make any harm with diffpairs routed on the bottom layer of an M2 card?

Moreover, there will be an FPC cable soldered onto the USB breakout pads on the bottom, which will be effectively very close to the bottom layer's traces:

Is this need to be considered during stackup decision, or as there is air in between the FPC and the bottom layer traces, there will be no (or just tiny) effect?

If I need/better to use 4-layer stackup, shall I add the current bottom traces to 2nd, or 3rd layer? 3rd layer seems better for having vias with shorter stubs. Manufacturer might be able to do backdrill, but I wish to keep things as simple as possible.

2. Designing layer-change with vias:

Can I make it better (not speaking of impedance managing, but better for signal propagation):

PCIe RX:

USB:

3. Length matching with meander:

Shall I finetune these (they look quite weird to me - if so, how?):

PCB manufacturer will do impedance control on these selected lines, and they will also validate the required impedance on the final unit.

So the goal of this question is to fine-tune my design to be suitable for high-frequency operation and further impedance-controlling (by the manufacturer).

Update

When defining the 4 layer stackup is this below structure suitable for my goals?

Update2 - final design

I have redesigned my board with 4-layers.

Stackup is the following:

1. Signal    - 38um
2. Prepreg   - 0.1mm (RO4450B)
3. GND       - 38um
4. Substrate - 0.406mm (RG4003C)
5. GND       - 38um
6. Prepreg   - 0.1mm (RO4450B)
7. Signal    - 38um

Prepreg has a nice solid 3.54±0.05 Dk value.

I wired the differential traces of USB and PCIe with 0.2mm trace and 0.254 spacing. Further impedance tuning will take place at the manufacturer's side.

I wish you to review my board layout, I tried recreating it based on all recommendations below.

This is the TOP (Layer1, signal):

Layer2 (GND):

Layer3 (GND):

BOTTOM (Layer4, signal):

Can you please review this layout? Can you spot any bad design?

Answer 1

Not providing an answer, but rather a formatted comment.

Tagging on to @tobalt answer, use at least a 4L board, your stackup should be

1 - Sig/PWR
2 - GND
3 - Sig/PWR
4 - GND 

All equal-voltage power rails should be VIA'd together at every 1/10 wavelength of the max operating frequency, and there should be a Ground-stitching via every 1/10 wavelength of the max operating frequency.

The max operating frequency is calculated by using

f.Max = 0.5 / Tr

where Tr is the rise time of the driving device. I don't know what it is for PCIe off hand.

Any time a signal changes layers, drop GND VIAs as close as possible to the layer change VIAs. Make your signal layer-change VIA annular-rings the same diameter as the track width, or the minimum required for your fabricator. Tear-drop your layer-change VIAs if you can.

The reason for the prescription here is that your signals need a few things to be happy:

1. A closely spaced (in the Z-axis) continuous reference plane. This accounts for the 4L stackup, and the ordering of that stackup. Layers are going to be pared up as (1,2) and (3,4). Layers (1,2), (3,4) will only have 0.004-0.006 inch spacing, between them, but layer pair (2,3) will have something like 0.030 inch spacing. That means that there will be a good, constant capacitor formed between layer-pairs (1,2) and (3,4). This makes impedance control possible.
2. The GND reference planes need to be an effective short at all interesting frequencies. GND stitching VIAs @ 1/10 f.max's wavelength will aid this.
3. GND vias next to the signal layer-transition VIAs. This allows the return currents flowing on the reference planes to change layers with the signal. Even though PCIe is fully differential, they are not galvanically isolated, they still reference the GND Reference plane, so whatever return current if in the GND plane has to change layers too. Placing GND vias next to the signal layer-change vias accomplishes that.
4. Teardropping VIAs is only necessary if the annular rings can't be the same width as your tracks. The reason for the teardrop is to "ease" the change in impedance over a larger area to reduce reflections that occur at a discontinuous width change.

The last comment I'll make is keeping the PWR and signal coplanar allows the POWER traces to have a good capacitive coupling to the GND plane, this will ensure the POWER rails have as good-as-possible power delivery to whatever device you're attaching.

Answer 2

A few reasons to go 4 layers. 1st, you'll never get 100 Ohm differential impedance at a sensible size on 2 layers. Note I'm assuming you need 1.6mm board thickness for the M.2, but I could be wrong. Even at 0.8mm it works out as 0.4mm width, which I is still too wide for 0.5mm pitch.

You also want 4 layers so you can have an uninterrupted ground plane under all your signals, in your current design they have to cross lots of splits which is bad.

It's also a recipe for cross-talk. Consider that REF_CLK0_N and SUSCLK run parallel, on top of each other for a part of the board. Pretty much-guaranteeing cross-talk between these two.

Use a 4 layer board
Top layer - RF signals
In1 - GND
In2 - GND
Bottom Layer - other signals

And respect that at much as possible. You might have to borrow one of the inner layers for a signal but do not break the GND plane under an RF signal, or under anything for that matter. Even your 3v3 power trace, which you might consider as DC, still needs a return path, ideally directly underneath it. You might think that it doesn't matter for a DC connection, but the current still has to flow back somewhere, and if you dont give it a nice path, it'll have to flow around to find a path. If this current flows underneath another signal trace, it can potentially couple into it. Remember that In1 and In2 are far apart, so In2 won't work well as your GND plane for your top layer, and the same with In1 and the bottom layer.

Particularly if this board is sitting above high-speed signals, I'd keep the bottom layer as devoid of high-speed signals as possible, it really depends on their speed as to wether you need to completely keep all traces off this layer.

It depends on the USB speed, whether I'd be worried about this, but you can always not run any traces on the bottom layer where you expect this cable to be. Air doesn't provide any shielding, so it could cross-talk. Equally, you can ensure that any traces cross this at a right angle to reduce this. Presumably there's a GND in the USB bus, so this could start to mess with your impedances a bit.

Answer 3

1. I think you must switch to 4 or more layers. The two layers can't provide good controlled impedance matching, the ground planes have slots that the lanes cross, etc. For such a simple (?) board you would use e.g. SGGS order so stubs are not a problem and each signal layer has a ground layer right under it.

2. Yes, you could add ground stitch vias for the data lanes when they change layer. And make sure vias also exhibit the same characteristic impedance.

3. Length matching may not be that important compared to proper impedance. The meanders are an impedance discontinuity even if the length matching is perfect.