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I have seen these a few times, but I don't know what the purpose is. Clearly the purpose is something else than just to invert the signal. Otherwise just one or two would be enough for that. Also, does this configuration have a name?

schematic

simulate this circuit – Schematic created using CircuitLab

SCCCCC
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    Can you give any context where have you seen this? In a real world circuit? In a simulated circuit? Which simulator? What is the circuit where this chain is in? – Justme May 10 '23 at 08:12
  • It is good to say that the inverter is the simplest logic gate (a repeater would be 2 inverters in series). Depending on what you have left on the board, you may as well see the same made with N-AND gates or something else. – fraxinus May 10 '23 at 19:18

7 Answers7

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It's an old trick to delay a pulse a certain amount of time, for ex. 100 nanoseconds. It's used to ensure that different circuits (or different parts of the same circuit) get the same digital logic signal in the wanted order. Let's assume the same pulse X is needed to start circuits A and B, but the right total effect needs that A starts before B. To guarantee it the designer lets B get X through a delay. The trick obviously was commonly seen in schematics say 50 years ago when complex systems were built of low integration level TTL or CMOS ICs. It's still used inside ICs.

The delay is not exactly known beforehand, because logic circuit manufacturers give "the propagation delay" in their datasheets with loose tolerances and the delay depends on operating voltage and temperature. But it can be good enough if certain minimum delay is a must, but tens of percents more is not harmful.

A transmission line based or an electroacoustic delay was used in cases where more accuracy was a must.

Hoogault
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    Perhaps worth noting that the delay is likely to track the delays of other parts on the same chip so if the need for the delay is related to the delays required for other gates to respond, it may even be preferable to have it variable vs. a precision fixed delay that is okay at room temperature but iffy when the chip gets hot. Or excessive at room temperature to make up for the longer delay required at a temperature extreme. – Spehro Pefhany May 10 '23 at 17:49
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    It's well worth noting. Thanks. – Hoogault May 10 '23 at 17:57
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    Note also that this technique is not very useful when you want a specific amount of delay between two points, because of the large variability in the prop delay through the NOT gate. But it can be used where you want a minimum, but not specific, delay between the signal reaching two parts of the circuit. – SteveSh May 10 '23 at 18:08
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    It was said too loosely "It can be good enough" Thanks for notification. – Hoogault May 10 '23 at 19:10
  • That makes sense. The signal that goes through the inverters is used to tell another IC to latch data from the data bus (because it doesn't have it's own circuit for reading data from the RAM chips). So, if that signal is triggered the same time reads are done from the RAM chips, the delay probably is intended to ensure the new data is on the data bus before the other IC latches it. – SCCCCC May 11 '23 at 18:17
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If the cascaded inverters are of same drive strength, it is for adding delay (as already mentioned in other answers).

If the inverters are increasing in their drive strength progressively, it is to drive a high capacitance load or a low resistance.

sai
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    To expand on this: The reason you need that increasing drive strength is because high drive strength means large transistors, but large transistors means high input capacitance for that stage, which requires a high drive strength on the previous stage--so you might cascade three or four or even ten or twelve stages of steadily increasing drive strength (=steadily increasing transistor size). This is essential for things like gate driver output stages, for instance. – Hearth May 10 '23 at 20:01
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    This technique is applicable at the chip design level (our IC designers do use thus technique to achieve a desired drive strength), but less useful use at the component level, IMM. – SteveSh May 10 '23 at 21:56
  • And, to achieve increased drive strength, it is far more common to parallel outputs from a chip like an 'ACT245. – SteveSh May 10 '23 at 21:57
  • @Hearth Why would high input capacitance require high drive strength, rather than (at most) a resistor to buffer the current? – Sneftel May 11 '23 at 13:06
  • @Sneftel Why do you think a resistor would help here? It seems to me that a resistor would just make things worse. – Hearth May 11 '23 at 23:16
  • @Hearth that wasn’t really my question. Why would high input capacitance require high drive strength, and hence laddering a dozen NOT gates? – Sneftel May 12 '23 at 07:09
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    That is done to get reasonable rise and fall time at every NOT gate output so that the input rise/fall times don't affect the output rise/fall times – sai May 12 '23 at 07:17
  • @sai Makes sense, thanks. – Sneftel May 12 '23 at 08:04
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Chaining inverters is sometimes done to push a digital signal's voltage towards the power rails. This could be done with just 2 inverters (or 1 if you don't care about the value being inverted) if inverters had infinite gain; however, real inverters have finite gain, which you can compensate for by just chaining more of them.

Here is an example voltage transfer curve for an inverter (from Wikimedia Commons): A graph of the voltage transfer curve of an inverter. It starts high and mostly level, begins a near-linear descent to a low value, and then remains mostly flat at that low level.

The slope of the near-linear part of the curve is, roughly speaking, the gain. If you put 1V into this inverter, you would see an output of around 2.5V. If you put that into the next inverter, you'd get around 0.75V. Then ~2.75V, then ~0.6V, and so on. Again, if the gain was infinite (a vertical line) you'd only need 1 or 2 inverters to get this effect. You could understand this as, essentially, a 1-bit analog-to-digital converter.

This is useful because CMOS logic consumes a lot of power when input voltages aren't near the rails, and current can rush through entire totem poles of half-open transistors from rail-to-rail. When interacting with a signal which you can't guarantee will have nice near-rail voltages, a chain of inverters can save power and make the circuit more robust.

This technique is often combined/merged with a chain of flip-flops, in order to cross clock domains (where you expect that your clock might instruct a flip-flop to latch a voltage which is currently being switched in the other clock domain.) Inverters before the first flip flop reduce the risk of it latching an indeterminate value, and the flip-flops themselves (being composed of totem pole gates with gain just like inverters) continue the effect.

Willa
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    Wouldn't a Schmitt trigger be a better option for this use case? – Edgar Bonet May 11 '23 at 10:12
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    @EdgarBonet Schmitt triggers are more complex circuits in CMOS logic where this technique is usually used - an inverter is the simplest CMOS gate with two transistors in a single totem pole, while the simplest CMOS Schmitt trigger uses 6 transistors in a geometrically complex arrangement. At a glance, I believe they would also have fairly low drive strength compared to an inverter composed of similarly sized transistors, since the path from rail to output goes through two transistors. The drive strength is much of what you want here, and inverters get you that in spades. – Willa May 11 '23 at 18:40
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Chaining/cascading on its own may not bring anything other than a delay which approximates to propagation delay times the number of gates. And with feedback it becomes possible to make oscillators or even flip-flops.

Sometimes the design of the IC requires the designer to place cascaded inverters (NOT gates) to bring a buffer functionality. For example, a BJT totem pole is a buffer and can be built with a complementary pair. However, a CMOS (MOSFET-based) totem pole is an inverter, so a cascaded pair is required to make a buffer.

Rohat Kılıç
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Another benefit of chaining NOT gates is to ensure a maximally fast rise time in the output signal when the input signal has a slow rise time. This usually only requires two or three NOT gates.

Phil Freedenberg
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As other answers pointed out an inverter chain or buffer is introduced to produce some delay. In digital integrated circuit design, adding buffers is one possible solution to fix hold time violations. Hold time is the minimum amount of time for which the data should be held stable at the input of a register after a clock event. A hold time violation occurs when the data changes before the specified hold time. To prevent the data from changing too quickly we add buffers in the input data path and introduce an artificial delay to meet the hold time requirement of the register.

Pavan Kumar
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It’s a fixed delay if the supply voltage is constant. It can also be a voltage controlled delay if the supply voltage is adjustable. That works quite well in the CD4000 family where then 3V to 12V delay change is about 5:1 ratio.

If there are taps off the inverters, then it’s a tapped delay line used to generate pulses with controlled relative timing. It’s often needed to get the last bit of performance out of discrete CMOS logic: the delays scale with supply voltage similar to the speed of the logic those taps control. It’s a building block for self-clocking logic.

Kuba hasn't forgotten Monica
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