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I managed to run an M.2 SSD (Samsung PM991A) in a TypeE socket with an adapter designed by CRImier (thank you):

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I wish to design my own board with similar functionality, and I can't understand one thing with this desing.

Here is the schematics:

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Here are two pinout guides:

The socket seems good on the schematic, however the card pins are not. Based on these above two pinout guides (for KeyE):

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It seems the schematic is mixing up the transmit and receive pairs. Or we have to swap these when designing a card (instead of socket)?

Another weird thing is this:

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Even if we consider swapping TX and RX a mistake: one is connected straight, and other is crossed. Is this legal?

The only sane reason I found is this way he didn't need to use vias for these wires:

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As this adapter is working correctly, I really wish to understand the reasons behind these swaps of RX<->TX and straight<->cross wiring.

Daniel
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  • I'm not familiar with PCIe/NVME in particular, but there *are* protocols where swapping + and - of a differential pair doesn't matter--1000BASE-T (gigabit ethernet) for example. I wouldn't be surprised if this is one such. – Hearth May 06 '23 at 22:10
  • I recall that the wires are positive and negative in SATA mode, but negative and positive in PCIe mode. And this is not SATA. – Justme May 06 '23 at 22:38

1 Answers1

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It all about choice of naming. PCIe Tx lanes from the upstream port should connect to the Rx lanes of the downstream port and vice versa (same as you would do for UART). This is done by the wiring of the NVMe device.

The adapter itself is doing the swapping of Tx and Rx twice. Once when the edge connector plugs into the motherboard, and once in the board itself. The NVMe then does the third swap as it plugs in to the adapter. This gives a total off three crossovers which is the same as just doing one. In reality two of those three 'swaps' don't exist, they are just the designers choice of naming. All is correct here.

Swapping of the +/- of a pair is called polarity inversion. It is fully supported by PCIe. During link training, the PCIe reciever detects this inversion and automatically corrects for it when decoding the data. This has no performance implications and is purely to aid routing.

Tom Carpenter
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  • Everything makes sense now. When I design my own card, is it *wise* to swap the RX/TX names for readability? I know it doesn't make too much difference, but officially, a card shall have RX pins where the socket has TX I guess. Are these names from upstream or downstream's side? For example an M socket's TX lanes are TX for upstream or downstream? – Daniel May 07 '23 at 06:43