Continuous current limiting with hot swap controller

Question

I am using a brushless DC motor which has its own integrated controller (nominal current 4 A at 24 V). To protect the motor, I'm willing to implement some current limiting circuit (e.g. with maximum allowed current 5 A).

The TI LM5069 hot swap controller (link), looks interesting, and ticks some other of my requirements as well (under and over voltage protection, short protection). From what I understand, it is initially intended to perform current limiting for a set period of time, after which it will consider that a fault happened and will enter a restart procedure. However in my case I would like to stay in current limiting mode for as long as the current is too high, without stopping (say for example when my motor is running at its maximum allowed power).

On this chip, the fault timer is set by a capacitor, which gets charged when current limiting is occurring, and by monitoring the voltage on the TIMER pin. See extract from datasheet:

8.4.3 Fault Timer and Restart

When the current limit or power limit threshold is reached during turnon or as a result of a fault condition, the gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation. When either limiting function is activated, an 85-μA fault timer current source charges the external capacitor (CT) at the TIMER pin as shown in Figure 25 (fault timeout period). If the fault condition subsides during the fault timeout period before the TIMER pin reaches 4 V, the LM5069 returns to the normal operating mode and CT is discharged by the 2.5-μA current sink. If the TIMER pin reaches 4 V during the fault timeout period, Q1 is switched off by a 2-mA pulldown current at the GATE pin. The subsequent restart procedure then depends on which version of the LM5069 is in use.

Questions:

• Instead of using a capacitor to set the fault period, would it be possible to pull the TIMER pin low (see image below) to prevent the chip from timing out when in current limiting mode?
• If so, would it be safe for the main MOSFET Q1? I assume it could be selected to handle the maximum allowed current over a long period of time?
• If not, is there an easy alternative to get the intended behavior, or would I need to design a dedicated circuit for it (e.g. something like these (Wikipedia), or as seen many times on this forum)?

Thanks in advance!

Answer 1

Instead of using a capacitor to set the fault period, would it be possible to pull the TIMER pin low (see image below) to prevent the chip from timing out when in current limiting mode?

The timer pin is not really strictly an input. It's a current source used to charge a capacitor over a period of time to control the power on sequence (see 8.4.1 Power Up Sequence), fault timer and restart (see 8.4.3 Fault Timer and Restart), and timing for the power/current limiting functions (see 8.3.1 Current Limit and 8.3.3 Power Limit). The particularly challenging part would be to accommodate the power up sequence and handle the restart sequence.

For the power up sequence:

the TIMER pin is initially held at ground. When the VIN voltage reaches the PORIT threshold (7.6 V) the insertion time begins. During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 5.5-µA current source, and Q1 is held off by a 2-mA pulldown current at the GATE pin regardless of the VIN voltage. The insertion time delay allows ringing and transients at VIN to settle before Q1 can be enabled. The insertion time ends when the TIMER pin voltage reaches 4 V. CT is then quickly discharged by an internal 1.5-mA pulldown current.

You could have a timer cap that is nominally connected to the timer pin and then use a controlled FET to short it to ground once the power up sequence has been completed. However, you would need a way of determining if/when that has happened an act appropriately.

The further trouble will be with the restart sequence as given by the below figure:

If using the timer capacitor bypass technique outlined above, you would need to re-connect it to allow the device to safely restart in the event of a fault. Faults like the "circuit breaker" and UVLO features would need to be recovered from with the restart sequence.

To answer the question directly: if you want to use this chip as you've described, it will take considerable effort using an MCU or other controller to bypass the timer capacitor only during the events you want. You'd need to track the states of the IC with a state machine and tightly control when the capacitor is bypassed and when it is connected. More effort than, in my engineering judgement, I think is warranted for the functionality.