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I have designed simple P-channel MOSFET circuit. It works well, but when low source power is applied (1 V), a glitch occurs in the output signal. I tried R, L and C component, but it didn't work.

What can I do to get rid of this?

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In fact, the above circuit is part of a complex circuit, and the actual simulation results are as follows

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winny
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aAa
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  • Why does it matter? – Tim Williams Apr 26 '23 at 03:54
  • That's normal. I forget what causes it though. I think it was something like the MOSFET source-drain capacitance charging up or something whenever you interrupt current. You're better off just learning what causes it than trying to deal with it. – DKNguyen Apr 26 '23 at 04:18
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    gate-drain capacitance – tobalt Apr 26 '23 at 04:18
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    (Change the term used: call it a *transient*. [Glitch](https://en.m.wikipedia.org/wiki/Glitch#Electronics_glitch) is used in (combinatorial) logic for 010 (101) sequences at an output when inputs change from one combination yielding a 0(1) to another.) – greybeard Apr 26 '23 at 06:17
  • As said, it's all about Cgd. However, out of any simulation, in a real environment, you'll have to consider the capacitance and inductance in the load, PCB tracks, etc. Then your final effect could be reduced (if well designed) or amplified (...) – LuC Apr 26 '23 at 07:42
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    @greybeard aree. I think "overshoot" and "undershoot" are even more descriptive. Anyway these are not "glitches". – danmcb Apr 26 '23 at 07:57
  • _"In fact, the above circuit is part of a complex circuit, and the actual simulation results are as follows"_ - Is the circuit you showed us an accurate representation of that part of the actual circuit? If not then please show us the actual simulation circuit. What are the characteristics of My? – Bruce Abbott Apr 26 '23 at 20:30

1 Answers1

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You are driving your p-channel MOSFET incorrectly

To drive it correctly, the input activation voltage must take the gate 5 volts (or more) below the source voltage. Then, return it to the source voltage when deactivating the MOSFET.

You currently have the activation voltage connected to 0 volts and that means that as the source voltage gets lower, the true activation voltage for the MOSFET gets lower. If the source voltage became zero volts then there is no possibility of the MOSFET activating.

However, due to the gate-drain capacitance, there will always be spikes transmitted from gate to drain when the input waveform has fast rise and fall times (high positive and negative slew rate).

Andy aka
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