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I simulated the Verilog code present in at this link that uses a Galois based ring oscillator to get truly random numbers.

The crux of its operation seems to be:

It is basically an LFSR type structure without the flip flops, so it is a combinatorial loop that runs continuously. The signal oscillates chaotically, when you combine several of these modules and XOR bits you get a truly random bit, since the jitter from each combines.

In the simulation, I naturally didn't get random numbers because it is deterministic and the conditions for jitter do not exist.

If I implement this on an FPGA (I am planning to do that soon,) how can I be sure that the conditions for jitter - delays, random noise - actually do occur? Some of the papers I read also suggest XORing the ouput of a GARO and a Fibonacci oscillator. What if the broad idea is correct but the LFSR chain length and the number of LFSRs need to increase to get random numbers? Is the only way to run the code, tweak it and find out?

JRE
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Abhishek Veeraraghavan
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  • *Or is the only way to run the code, tweak it and find out?* <-- why have you not done this yet? It seems the only sensible thing to do (in my mainly analogue humble opinion). – Andy aka Apr 16 '23 at 18:35
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    I'm not an expert on this, but everything I've read about getting _truly_ random numbers is that it's not easy. there's all sorts of natural phenomenon that will influence your attempt at randomness in some deterministic way (i.e., your "chaotic" oscillator may inadvertently synchronize to some signal that's harmonically related to your read clock). I suggest deep study. Or start collecting lava lamps and video cameras. Or something. – TimWescott Apr 16 '23 at 18:37
  • Andy aka - I don't have my hands on an FPGA at the moment, will try it out soon. TimWestcott - I get your point. I am okay if there is some bias and if my numbers aren't truly random. What I wanted to know is if there was a way to differentiate between incorrect logic or code versus things failing because of other reasons. Or if there was some kind of information about how much the likelihood of getting random numbers/jitter increases based on the length of the LFSR chain or the input clock frequency. I have read a little bit about this. Thanks for the comments – Abhishek Veeraraghavan Apr 16 '23 at 19:24

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The really adequate way to do this would be to simulate it in a circuit simulator, or in a general-purpose ODE simulator, complete with adequate noise sources.

A circuit simulator is probably best, unless you really want to abstract the behavior away from the fact that an FPGA is, after all, an electronic circuit.

That way could could simulate things like deterministic disturbances on the power supply lines causing the behavior to be less than fully random.

Unfortunately, this requires either guesses that are at best only approximate, or a deep knowledge of how the FPGA works that's probably highly proprietary.

TimWescott
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  • Tim, by circuit simulator which one or what kind of simulator are you talking about? By ODE simulator do you mean an Ordinary Differential Equation simulator? – Abhishek Veeraraghavan Apr 17 '23 at 14:49
  • Try searching on "circuit simulator". I think the breadth of the answers would give you an idea of what's available. By ODE simulator, yes, I mean an Ordinary Differential Equation simulator. – TimWescott Apr 17 '23 at 15:31