ULN2003 low-side switch electrical characteristics

Question

ULN2003A

So I'm currently exploring low side switches. I started off with an NMOS transistor array IC (Open drain), to develop a better understanding I've tried to understand the Darlington transistor array (Open collector) implementation as well. I have some doubts

1. Pretty basic, but for switching action the transistor operates in cutoff and saturation modes. Therefore if the Input is LOW, the BE of the first transistor wouldn't get forward biased therefore leading the second transistor in the pair to be off as well. So the collector potential would be equal to that of the floating output. So if I was to have a pull-up resistor then i'd say that for LOW input my load is getting powered from Vcc(external) Output HIGH.

   Q. What are the input thresholds? V(IL) or V(IH) as per the snippet of the electrical characteristics? Like whats the thresholds to be considered as input high or low to the transistor is it defined by V(be) itself?

2. In saturation, the V(ce) is around 0.9V. Consider V(be) of the first transistor 0.7V drop, and the V(ce) in saturation is roughly 0.2V or so since its an common collector config the V(ce) is 0.9V.

Now as seen in the datasheet V(ce) varies with I(c) fair enough, is I(I) the base current? Only that'd make sense as I(b) increase would still lead to I(c) being fixed to I(c sat) when the transistor operates in saturation.

3. What is V(I(on)) except what the name suggests, is it V(bb) ?

4. Similarly V(OH(on)) is it analogous to V(DS) in a FET when its input is high?

5. Could you explain I(off) and I(I)

PS(I feel like I've understood the working but I can't understand the datasheet parameters except V(ce), I(cex) & clamping parameters

Reason for being in saturation -> Say input voltage is high enough, thereby current & voltage through base limiting resistor is enough to forward bias the BE junction.

For the NPN to be in saturation, BE & BC junctions must be forward-biased. Since the collector is floating or open. The output pin(collector connected to output) as per the working sinks current. So anyway Collector is at much lower potential than whatever is found at the base of the transistor therefore forward biased hence we can conclude that the transistor is fixed to saturation when it is on. (assuming there's some load being driven by external V_cc in the presence of pull up resistor. is the above right?

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1. The output pin is internally connected to the collector of the BJT. I'd like to know, based on this, if my provided reasoning for the transistor being in saturation while sufficient V(BE) is applied, is correct or not.

2. I(I) being 0.93mA this is the input current associated with V(I). 0.93mA is enough to turn on the darlington pair with context in BJT terms since I(I) can roughly be said I(B). So reframing ~0.93mA is sufficient base current to turn ON the pair (in saturation).

3. By two of V(BE) wrt input threshold you mean two potential drops worth, would the threshold be near to 1.4V (+-)

4. With regard to V_Ion, I understood what you said, but paying attention to test conditions V_CE is 2V. Granted it could be a possibility that V_BE > 2V (for saturation). But wouldn't it lead to damaging the IC (as diode between Base & emitter can only handle 0.7V). Also the achieve the advertised I_C of 500mA (keeping within the simultaneous output limit) I just keep increasing V(I)?

5. What is meant by full saturation. Do you mean deep saturation where the hfe is fixed -> based on which we calculate other parameters such R_B which ensures that the transistor can never go into active region.

Answer 1

1

Don't confuse "current flowing through the load" with "collector potential". If the load is connected between some fixed high potential and collector C, and is "powered" when current flows through it, that's when C is at a low potential, and the input is high.

That means from a voltage perspective, this thing inverts. From the perspective of load current flowing or not, it does not invert. A high input switches on current, but brings C low in potential.

To get appreciable base current into the first transistor requires that the input potential rise above two \$V_{BE}\$ drops, 1.4V or so. Input current will be about

$$ I_I=\frac{V_I-2V_{BE}}{R_B} $$

The datasheet declares that with input \$V_I=3.85V\$, then input current \$I_I\$ should be 0.93mA, typically. Lets check:

$$ I_I=\frac{V_I-2V_{BE}}{R_B} = \frac{3.85V - 2\times 0.7V}{2.7k\Omega} = 0.91mA $$

Close enough.

Don't forget that this is still an analogue system, there's no feedback to control switching thresholds, or gain. Therefore you are correct to suggest that the input switching "threshold" is defined purely by \$V_{BE}\$ (two of them, in fact).

That is not to say that there is a clear threshold, since as I said, this is still an analogue system at heart, with an associated "linear region" of operation.

A darlington pair has huge current gain, and 0.93mA is way more than enough to switch on the the pair. The figures \$V_I\$ and \$I_I\$ only tell you what input current will actually flow given some input potential. They say nothing about what exact input potential is sufficient to actually saturate the darlington pair.

For that information, we refer to \$V_{I(ON)}\$, which is a collection of potentials that the designers deem (conservatively, with enough margin to cover their asses, no doubt) sufficient to fully saturate the output transistor, given some expected collector current.

Naturally, since \$I_I\$ is heavily dependent on \$V_I\$ (see the equation above), and collector current is a function of input current \$I_I\$, you should expect the necessary input "threshold" voltage to vary somewhat with required collector current.

2

Are you asking, or telling us why \$V_{CE}=0.9V\$? Your assessment is correct.

As for \$I_I\$ being base current, that's roughly correct. I say roughly because the 7.2kΩ resistor will divert some input current away from the base. We can estimate how much, by assuming that the voltage across it is \$V_{BE}=0.7V\$:

$$ I_{7k2} = \frac{0.7V}{7200\Omega} = 100\mu A $$

By KCL, base current \$I_B\$ will be input current (calculated from \$V_I\$ using the above equation) less this resistor current:

$$ \begin{aligned} I_B &= I_I - I_{7k2} \\ \\ &= \frac{V_I-2V_{BE}}{R_B} - 100\mu A \\ \\ \end{aligned} $$

3

As mentioned before, \$V_{I(ON)}\$ is the minimum input potential (for some required collector current) that the designers guarantee will cause the transistors to saturate. For example, if your load will draw 200mA, then \$V_I\$ must be at least 2.4V.

That's doesn't mean that less than 2.4V won't work, it might. The designers will bet their jobs that \$V_I\ge 2.4V\$ will cause up to 200mA of collector current, even if the actual figure for your particular device is less than 2.4V.

4

The term \$V_{OH(ON)}\$ doesn't exist, since a "high" output occurs when the transistors are off. Refer to (1) above for my reasoning.

The value shown for \$V_{OH}=V_S-20mV\$ is simply telling you that when the transistors are off, collector potential can (eventually) rise to within 20mV of whatever potential is at the top of the load. Whether it actually gets there, and how long that takes, depends entirely on what you've connected to the collector, and how.

This figure is just saying that as long as you don't do anything weird with the collector (like pulling it down to ground via a resistor, or otherwise constraining its potential), the collector is free to rise nearly all the way to \$V_S\$, which I presume is the potential at the top of the load.

\$V_{COM}\$ notwithstanding, that is. It can't rise much above \$V_{COM}\$ due to the diode there.

5

In the "off" state, where minimum collector current is flowing, and collector potential is at its greatest, \$I_{I(OFF)}\$ gives you an upper limit to input current \$I_I\$, which is 65μA.

There will be some input potential that will just begin to turn on the transistors, and as long as the input voltage is significantly less than that, so that the transistors as "off" as it's possible for them to be, some input current may still be flowing.

This figure \$I_{I(OFF)}\$ is the worst case input current you will encounter, in the off state.

I think I described \$I_I\$ in sufficient detail in section 1.