5

I compiled the IP core library in Modelsim. The library from Xilinx is installed on my computer and I also created a ROM using the Xilinx tools. However when I simulate the IP core I find that fetching data from the ROM will delay the simulation by one clock cycle. How can I deal with it?

I don't want to write a second set of code, one for the simulation and one for downloading into the Spartan-3E. I program in Verilog and the following is the test bench for the IP core:

`timescale 1ps / 1ps
module InstrMem_tb  ; 
    reg    clka   ; 
    reg  [31:0]  dina   ; 
    reg  [7:0]  addra   ; 
    wire  [31:0]  douta   ; 
    reg  [0:0]  wea   ; 
    InstrMem  
      DUT  ( 
             .dina (dina ) ,
             .addra (addra ) ,
             .douta (douta ) ,
             .wea (wea ) ,
             .clka (clka ) ); 
    initial begin
        wea = 0;
        dina = 0;
        addra = 0;
        clka = 0;
    end

    always
        #50 clka = ~clka;

endmodule

I can only fetch the data at address in the IP core named InstrMem at the second posedge.

zijuexiansheng
  • 171
  • 4
  • Glad you found the problem. Rather than editing the question the preferred way here is to post the solution as an answer to your own question. That way it doesn't look unanswered and it may help future visitors. – PeterJ Apr 20 '13 at 12:10
  • Well, since I'm just a novice here, my reputation is too low to allow me to post my answer of my own question. Mybe I should do it later. – zijuexiansheng Apr 20 '13 at 14:04
  • I didn't realise that was limited, question was good in general so I just gave you upvote and you should get there soon enough. – PeterJ Apr 20 '13 at 14:13

1 Answers1

2

I suddenly found what's wrong with my program. It's the timescale. I set the timescale to be 1ps / 1ps, which is not enough for the ip core to work correctly. When I change the timescale to 1ns / 1ps, it works correnctly.

zijuexiansheng
  • 171
  • 4