How to zero the output baseline of an op-amp-based voltage amplifier?

Question

There is a constant leakage current flowing through the detector (SiPM) shown in the circuit below. It causes a constant shift of the baseline in the output of the voltage amplifier. Is there a way to make the output baseline adjustable or very close to zero?

Edit:

• I am not interested in the DC component in the signal.
• The op-amp is powered by a single USB connection for convenience.
• A SiPM is an array of multiple avalanche photodiodes. At room temperature avalanche will happen in ~10 kHz even without any light. This creates a constant reverse leakage current through the device. When the device is hit by many photons at the same time, a current pulse larger than the dark current will appear. C5 is used to supply charges needed to maintain that short-lived large current pulse.
• The final goal is a transimpedance amplifier that picks up sudden current changes from the detector (SiPM) and outputs it as a voltage signal with a baseline at zero. If there is a better solution than the one shown below, that is acceptable too.
• I am aware of charge-sensitive pre-amps. But I am afraid of the constant pulse piling up at their outputs due to the existence of dark pulses from a SiPM.

Answer 1

I'm no expert in SiPM, but based on quick read at this article (https://www.onsemi.com/pub/Collateral/AND9782-D.PDF), it appears that if you take the input signal from the "fast output" pin of the SiPM, then this signal is effectively AC coupled.

For now I'm going to ignore that and just focus on your schematic as it appears.

First, we need AC coupling to prevent the (+) input of the amplifier from sensing DC. A resistor to ground then follows in order to form a high-pass filter and bias your input to some voltage. If your supplies were bipolar, then you could simply connect the resistor to ground. However, your supplies appear to be unipolar; therefore, you need to connect that resistor to some middle voltage, perhaps 2.5V might be a good idea.

Second, any op-amp has an equivalent voltage offset referred to its input. You can ignore everything from your input signal and just consider how this DC signal will be amplified towards the output by a factor of 11 (the non-inverting gain of your op-amp). To avoid this, you need to make the equivalent impedance of R6 infinite at DC. This can be achieved by simply adding a capacitor in series with it to ground. It'll also define, partly, your -3dB frequency as a high-pass.

There are also other considerations. The value of this high-pass resistor must be large. Why? Assuming the 100nF is a short at your frequencies of interest, then your SiPM is effectively connected to AC ground. However, your SiPM has a parallel capacitive impedance.

If you refer the current noise of this high-pass filter resistor to the input (I'm assuming you have replaced R1 by a coupling capacitor). Then you'll effectively have a voltage noise due to the coupling capacitor (which can probably be ignored at your frequencies of interest), and another voltage noise due to R5.

How do I know this? You can use the Blakesley shift theorem (a very old theorem that is criminally ignored by most mainstream texts, unfortunately). You can check this answer I wrote where I show how to use this theorem to calculate input-referred noise effortlessly. Hopefully, then you'll be able to follow what I'm saying above.

Here's also a GIF I came up with to show how to use this Blakesley shift theorem without much text. It's not exactly your schematic, but I think it'll help you quite a lot:

This noise voltage due to R5 I mentioned earlier is basically amplified towards the output by your 1 + R3/R6. You could argue that is somewhat low-pass filtered due to the capacitive impedance of your SiPM to ground, but I'm guessing this is happening at very high frequencies that you won't be saved by it at your frequencies of interest.

Answer 2

This offset that you are trying to eliminate might actually be a good thing, because no op-amp is really capable of producing an output potential equal to its lower supply, even so called "rail-to-rail" devices, or ones that explicitly claim to produce outputs right down to the lower supply.

If you use a single-ended supply, with the op-amp's lower supply at 0V, a more realistic lower limit to the output might be +50mV. Your attempt to remove the offset, to obtain a quiescent output of exactly 0V (in the "dark"), amounts to asking the op-amp to produce an output of 0V, which it simply cannot do.

The output, then, of your op-amp has a lower constraint, but so does the input. Many op-amps will not behave well when either of their inputs falls below the lower supply potential. Some (older models) will even send their output right up to the maximum possible, a phenomenon called "phase inversion".

This is why in most tutorials and documentation, the op-amp usually has a negative supply too, to avoid these inconveniences. Ironically, in your circuit, the slight positive offset at the input that you are trying to eliminate might be the only reason the thing works at all.

If you did have a negative supply for your op-amp (even if only slightly negative), then the output and input ranges can include 0V, and removal of the DC offset component is trivial. Simply decouple the feedback path from ground, with capacitor C6 here:

^{simulate this circuit – Schematic created using CircuitLab}

It will take a few milliseconds following power-on for the output to settle to 0V, while C6 charges up to the input signal's mean potential. Like all AC coupled stages, if input potential remains higher than baseline for an extended period, this AC coupling capacitor will charge over time to the new mean, and when the input returns to its usual level, the op-amp output will be momentarily negative. And vice versa.

If you don't have a negative supply, then I'm sure you don't want to have to add one, and you're not alone. But the sad truth is that no op-amp can output a potential very close to its negative supply, and this has consequences for any stages that follow, including any analogue-to-digital converter (ADC).

No subsequent stage should expect to receive a zero potential signal, and if that stage happens to be an ADC, then you have to accept the reality that this ADC input will never see less than +50mV (well, maybe less, but that depends on the op-amp model). In other words, you must expect to lose some of the lower counts of the ADC's full conversion range. If the following stage is another amplifier, then you must deal with the fact that the incoming signal will never be zero.

So, you don't have a negative supply, and you don't want to make or add one. All is not lost. You can create a new "supply rail" somewhere between the the ones you already have. One at, say, +0.1V. Then you may use this new voltage source as your "surrogate ground" for all the analogue stuff. If all analogue potentials are considered relative to this +0.1V, then it's as if you now have op-amp supplies of +4.9V and -0.1V. The op-amps don't care what you call "analogue ground".

There's one major requirement for this new "analogue ground"; that it be low impedance, low enough to stay fixed at +0.1V despite any load that may be connected to it. Here's one way to achieve that:

^{simulate this circuit}

With negative feedback, the output of an op-amp is very close to zero, and will resist very strongly all attempts to shift it. However, most op-amps can only sink or source at most 10mA or so at their output, so we must still take care not to ask for more than that.

This "analogue ground" AGND can be used by any and all subsequent stages as a common point of reference, such that any signal with this potential is considered to be zero.

Now let's rebuild the above AC coupled, offset-cancelling amplifier, employing this new analogue ground:

^{simulate this circuit}

I have told op-amp OA1, your amplifier, that the new reference baseline is AGND at +100mV. I have removed C6, and moved AC coupling to the input, a task now performed by C7 and R12. This ensures that quiescent output potential is also +100mV.

All op-amps following this stage can share this same baseline, and since none of them are being asked to produce 0V output, everybody's happy. If there's an ADC at the end of the chain, it too will see a baseline of +100mV, and you will have to compensate for this in software. Here I add a second gain stage, and give both stages a gain of 48, for a combined gain of 2300, and yet the output still has a quiescent potential of 100mV:

^{simulate this circuit}