Driving high-side MOSFET with another voltage source

Question

I am trying to create a negative voltage source with a high-side MOSFET using another voltage source which is 4 V higher than the MOSFET's drain voltage.

In the schematic Q3's drain has 12 V and gate sees 16 V pulses. In this design, is 16 V enough for driving Q3 or will it need a higher voltage on the gate?

Feedback is going to an MCU and I used a voltage divider. In the worst case the feedback sees 12 V which is too much for feeding back to the MCU and in the best case feedback sees 1.09 V. Is there a better way to return feedback to the MCU from a negative voltage source?

Answer 1

Sadly, 16V is not high enough, but neither is 0V low enough for Q3's gate.

Q1 is supposed to drive Q3's gate high, but its base-emitter junction drops 0.7V (it's operating as an emitter follower, don't forget), leaving only 15.3V at the gate, for \$V_{GS} = 3.3V\$. Q3 could require \$V_{GS}=4V\$ to just begin switching on. To switch it on and pass significant channel current (without dropping significant voltage between drain and source), I expect you'll need much more than 16V at its gate.

Fig. 1 on page 3 of this datsheet shows you what voltage \$V_{DS}\$ you can expected the channel to have at various \$V_{GS}\$ and channel currents. For instance, looking at the curve for \$V_{GS}=4.5V\$, you can see that at 3A channel current, you lose 0.4V. I think you should be aiming for \$V_{GS}=6V\$ at least for this application, which implies a gate potential of 18V.

The worst issue you will face is that by using an N-channel MOSFET high-side, you are operating it common-drain, as a source follower, whose source is never further than 4V below the gate; \$V_S = V_G-4V\$. You bring the gate down to +0.7V (not 0V, again because Q2 is an emitter follower), and Q3's source gets clamped to a minimum of -3.3V. This is bad, since the source (cathode of D1) must be free to swing to -12V in order to charge C1.

You must therefore drive Q3's gate with potentials +18V and -8V or so, which is quite the dilemma. The NMOS solution in the answer by "Kuba hasn't forgotten Monica" can be simulated; watch how gate potential swings between these extremes. The easiest solution to both of these problems is to use a P-channel device, which you can switch with 0.7V and +11.3V.

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Update: I made it sound like PMOS answers all the problems, but be aware that in this setup it's easy to get \$V_{GS}\$ to exceed ±20V, which is a common maximum for many MOSFETS. Either make sure you use a device which can handle ±24V between gate and source, or take measures to protect that gate.

Answer 2

I see several problems:

1. Gate drive needs to be referenced to output voltage, i.e. the low level of the gate voltage must follow the negative output level. Otherwise, the mosfet will stop turning off when the output goes past -3V or so.

2. +16V is not a high enough gate drive, given the Vth spread. A bootstrap voltage generator is needed.

3. The gate driver you propose is so slow that it will cook the mosfet due to conduction losses. Use an IC gate driver, or a suitably fast discrete solution (see below).

4. There's no inductor current sense. The upper duty cycle limit will have to be rather controlled based on the output voltage. When V(OUT)≈0V, only rather tiny duty cycle will let the inductor current cross 0 - otherwise the inductor will saturate due to runaway positive current.

   The D.C. has an upper limit that goes up as the output voltage goes down. That's a hard limit to avoid inductor current runaway. The duty cycle can then be reduced as the voltage control loop gains control.

5. Whatever efficiency savings might have been there by using an NMOS were obliterated by poor gate drive. Of course, it's not as if a PMOS can have slow gate drive either, just that the gate voltage swing would be smaller, so there would be less gate switching losses.

NMOS Variant

Tirst' let's address the circuitry around the switch, and then we'll tackle the gate driver.

^{simulate this circuit – Schematic created using CircuitLab}

The boost voltage relative to ground is the sum of the difference between the input voltage and output voltage - just shy of 24V.

Now, we need a good gate driver. The one you got is very slow and will make the mosfet run very hot. The driver below produces ≈50ns edges into a 2nF gate capacitance. The input is 3.3V CMOS logic.

Q5 and Q6 drive away the stored base charge, since Q7 and Q8 saturate.

^{simulate this circuit}

This gate driver's low output level must be below about 0.5V, and the high level must be above about 2.5V. Within these limits the driver will work with other voltages too, e.g. 0V-12V, etc.

PMOS Variant

To save on gate switching losses in M1, it should be a PMOS - then we get rid of 16V and BOOST circuitry, and the gate driver's output levels change to 0V-12V:

^{simulate this circuit}

And the gate driver:

^{simulate this circuit}