3

I was reading the hardware design manual of the WF200 WiFi processor. On one page they say:

If possible, use an isolating ground metal between the crystal and VDD traces to avoid any detuning effects on the crystal caused by the nearby power supply and to avoid leakage of the crystal/clock signal and its harmonics to the supply lines.

Does it mean that I should have a keep-out zone like this? As you can see, the XTAL_I (input) and XTAL_O (output) and the complete crystal is sourunded by an isolating area. Only GND is allowed to enter the area.

Question:

Is this what the manual is trying to say? That this benefit the design?

enter image description here

Update: enter image description here

Update 2:

enter image description here

euraad
  • 1,025
  • 11
  • 30
  • similar earlier question (probably not a duplicate): https://electronics.stackexchange.com/a/5608/7036 – Nick Alexeev Mar 16 '23 at 21:18
  • @NickAlexeev He is sourounding the crystal with a GND plane. I cannot do that in this case. – euraad Mar 16 '23 at 21:52
  • The idea is to reduce capacitive coupling between the oscillator signal wires and other signals wires by placing a ground trace between them. The ground should be routed so that no current passes through it. Only one connection to the MCU ground or ground plane. – RussellH Mar 16 '23 at 21:59
  • @RussellH You mean like this. Se updated post. – euraad Mar 16 '23 at 22:38
  • 1
    @euraad Out of curiosity, why is pin 2 of the crystal connected to ground through a resistor? What's the model for the crystal? – Nick Alexeev Mar 17 '23 at 02:31
  • @NickAlexeev See page 19 of the datasheet above – euraad Mar 17 '23 at 06:10
  • @euraad Page 19 in the user guide only displays the PCB layout. It doesn't give any explanation for the resistor. – Nick Alexeev Mar 17 '23 at 14:50
  • @NickAlexeev Yes, I know. But perhaps it must be a reason to have a resistor there as well? – euraad Mar 17 '23 at 15:37
  • @NickAlexeev But what do you think about my last image I posted in my OP? – euraad Mar 17 '23 at 15:38

1 Answers1

3

The wording in the manual is a bit odd, "isolating ground metal", which might be better phrased as "grounded copper". In effect, the manual is saying to ensure that as far as possible, between the clock and any power rails, there is some grounded copper in between. This will ensure any capacitive coupling is between the xtal and the ground, not the xtal and the rail to reduce if not remove the possibility of the clock leaking onto the power rail. Similarly, it will ensure the power rails don't "detune the Xtal" ie negatively affect it, presumably either through capacitive or resistive coupling.

You might use a similar sort of thing in various scenarios, sometimes even the Mega Ohm resistive paths that can be present on a circuit board can cause problems, so you make sure the ground encircles the sensitive net.

In your specific example, replace the keep-out zone, so it excludes traces but allows the ground pour. Or personally, I would just make a note, perhaps even a colored box on a non-technical layer to remind me. Obviously, your current design rules will prevent copper between pads 8 and 9 of the chip, but you could still shift the Xtal a bit to the left to allow the ground pour to run right up to the pads. Currently, there's no ground between XTAL_0 and VDO_DIG, which is the opposite of what the manual is asking for.
[edit] I missed your update while typing my answer. The second image, while it does get the ground net all the way around the Xtal, is a poor choice as it forces the return current through a choke. You can just use one ground pour, you don't need the gap. enter image description here

LordTeddy
  • 1,742
  • 18
  • Thank you for your answer. Se my updated image. – euraad Mar 16 '23 at 22:38
  • Can you give my an image about "Ground pour" ? – euraad Mar 16 '23 at 22:49
  • You ask, and Microsoft paint helps me provide! – LordTeddy Mar 16 '23 at 22:57
  • But did I not make a clearance ? – euraad Mar 17 '23 at 06:14
  • No, not like that. I just mean that in my drawing, because I've used paint (the drawing program) to fill in the gaps, the GND pour is physically touching the nets XTAL_0 and _1, which is obviously wrong, you need that clearance like you have everywhere else in the pour. From your image update 2, remove the 2 keepout areas you've drawn, just delete them, and refil your GND pour and you'll be done. – LordTeddy Mar 17 '23 at 15:47
  • So I only need GND around my crystal? – euraad Mar 17 '23 at 18:41
  • It's difficult to understand what you are trying to say. Can you show me an example picture? – euraad Mar 17 '23 at 18:42
  • Look at the pitcure in my answer, the ground pour should be like that, making sure the GND is between the XTAL nets and any others. – LordTeddy Mar 19 '23 at 17:09
  • So...ground pour is that you have removed the ground? But according to the datasheet, I need to connect the shell of the crystal to the ground. – euraad Mar 24 '23 at 08:31
  • I can't see what you're not getting. The crystal is clearly connected to GND in my image. – LordTeddy Mar 24 '23 at 12:31
  • But now you have removed the eletrical clearance? It's supposed to have a boundary like a wall of no GND around the crystal. – euraad Apr 03 '23 at 18:34
  • No, the opposite, there should be ground surrounding the crystal. – LordTeddy Apr 04 '23 at 11:12