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This video describes a decoder circuit for Manchester encoded signals, and the same circuit is also mentioned in this article. I can understand the circuit, and I'm interested in what different approaches exist for creating the delay in the delay circuit (should delay the clock to D flip flop by 1/4th period, since that always samples the correct non-return-to-zero value. ) I also note that the NRZ is shifted 1/4th of a period, but the XOR to recover the clock rate still works, the rising edge is still synchronized, it just has occasional clock pulses with a different duty cycle. The delay circuit delays the clock by 3/4ths of a period (to sample 1/4th period too early. ) How is that achieved, usually?

enter image description here

I've simulated the circuit in VHDL, with a delay circuit that already knows the clock rate, and then it works. But that is kind of meaningless because the point of Manchester is to recover the clock without knowing it. I was curious to if there are solutions where the clock is delayed 3/4ths of a clock signal using only the clock signal in the Manchester encoded signal. Or as close to that as possible. And if such solutions can adapt dynamically to different frequencies.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder is
    Port ( clk    : in STD_LOGIC;
           mcr_enc: in STD_LOGIC;
           clk_rec: out STD_LOGIC;
           NRZ_rec: out STD_LOGIC
           );
end decoder;

architecture Behavioral of decoder is

signal NRZ : STD_LOGIC := '0';
signal REC_CLK : STD_LOGIC := '0';
signal clk_rec_buf: STD_LOGIC_VECTOR (7 downto 0)  := "11101111";

begin
    NRZ_rec <= NRZ;
    clk_rec <= REC_CLK;
    REC_CLK <= mcr_enc XOR NRZ;
    process (clk)
    begin
        if rising_edge (clk) then
            if clk_rec_buf(5) = '0' and clk_rec_buf(4) = '1' then
                NRZ <= mcr_enc;
            end if;
            clk_rec_buf <= clk_rec_buf(6 downto 0)&REC_CLK;
        end if;
    end process;
end Behavioral;

This is a pretty broad question. I'm very interested, if anyone is interested in explaining the answer to me and understands what I ask and why.

BipedalJoe
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    "The point of Manchester is to recover the clock without knowing it" is not precisely correct. Manchester decoders assume that the clock rate is known by the receiver. It allows clock and data to be transmitted over a single pair. A good discussion is at https://www.renesas.com/us/en/document/dst/hd-15530-datasheet?r=496341 . – John Birckhead Mar 15 '23 at 22:58
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    For another take on Manchester encoding, look up Mil Std 1553, which uses Manchester encoding. While this is a old standard going back almost 50 years, it is still being used on new high tech programs, including the James Webb Space Telescope. – SteveSh Mar 16 '23 at 00:22
  • The point is, the delay doesn't have to be all that precise. Anything between, say, 60% and 90% of the bit period will work just fine, with somewhat reduced tolerance of jitter on the input signal. Put another way, with a fixed delay, you can decode a range of bit periods that's +/-20% of your nominal value. – Dave Tweed Mar 16 '23 at 02:12
  • SteveSh, John, Dave, thanks, all good comments, will look into what you all said later today – BipedalJoe Mar 16 '23 at 12:25
  • @DaveTweed very good point and maybe that de-mystifies it all enough for me. Of course sampling anywhere within half a clock cycle early works (but with less margins for jitter), did not think about that. Have tested in my VHDL simulation too with 1/8th too early, and 3/8ths, and works great. Cool stuff. I'd still like to understand the type of circuit often used for creating the delay. Perhaps John or Steve's comment addresses that, will have a look at what they mention later today. – BipedalJoe Mar 16 '23 at 15:05
  • I may be mistaken, but there is nothing in Manchester encoding that requires a clock on the receiving end. A Manchester interface is self-clocking. All that's needed is the proper delay on the receiving end, per the picture posted by OP, to create the clock from the incoming data stream to use for sampling the incoming data. – SteveSh Mar 16 '23 at 16:00
  • Steve, don't think anyone said anything else, the question is about how the delay is usually done and adjusted to the clock in the signal. What I meant with "sampling anywhere within half a clock cycle" is that the right value for the bit stretches over half a clock cycle (first half of it), then it jumps to the opposite value for the other half. – BipedalJoe Mar 16 '23 at 21:57
  • At the moment (I'm a noob in terms of experience with these things) I'm thinking a 555 timer with a potentiometer to regulate the delay might be the easiest thing to try (Falstad.com uses it in its Pong hardware implementation... ) Since the signal to the D flip flop is discrete edge signal, and it is what has to be delayed. The whole wave form does not have to be delayed, just the rising edge. – BipedalJoe Mar 16 '23 at 22:22
  • seems like 555 timer cannot delay longer than input high pulse. Anyhow, I think I get the big picture now. The article I linked to in question links to https://www.infineon.com/dgdl/Infineon-AN2358_Manchester_Decoder_Using_PSoC_1-ApplicationNotes-v06_00-EN.pdf?fileId=8ac78c8c7cdc391c017d073743355aa8&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files&redirId=File_1_3_1544 that uses a counter with its own clock set to 16x clock in manchester data, simple enough and as Dave said it does not have to be super precise. Thank you all for your comments. – BipedalJoe Mar 17 '23 at 00:11
  • More like a UART interface than a Manchester. – SteveSh Mar 17 '23 at 01:09
  • Possibly. I thought of UART too. I'll have a look at Mil Std 1553 eventually that you mentioned. – BipedalJoe Mar 17 '23 at 20:50
  • According to ChatGPT Mil Std 1553 uses a phase locked loop for the delay, that's also what user4574 suggested and I've come across them before (but don't understand them well yet) so I assume that might answer my question. – BipedalJoe Mar 17 '23 at 21:11
  • I now got it working with a 555 timer too (in Falstad), with potentiometer for delay. And PLL being a lot more complicated is something I'll look at in the future. thanks all for help. – BipedalJoe Mar 17 '23 at 23:14

1 Answers1

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If you are using an FPGA, then there are a few ways to create a delay.

  1. Shift register delay: If you have a clock source "clk" that is 8X the frequency of the expected frequency of "clk_rec" then you can just sample the incoming signal "mcr_enc" into six flip flops to create the delay.

  2. Use a DCM tile: In Xilinx 7 series parts there are DCM tiles that can generate a clock using a PLL. The multiply and divide ratios and phase are configurable at runtime. It's possible to make logic to adjust the DCM output clock frequency to, on average, match the incoming transition rate.

    Furthermore, the clock feedback input to the DCM can come from an external pin. So, one should in theory be able to make the PLL directly track the Manchester encoded bit rate (so long as the bit rate falls within the allowed frequency range for the PLL).

user4574
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  • not in an FPGA, just generally. I only included the VHDL code to show that I’d at least tested to simulate the circult, sometimes forums like this want you to show what effort you made yourself to discover the answer on your own – BipedalJoe Mar 16 '23 at 12:23
  • Well even without using an FPGA, the approach of using a VCO and phase detector to make a PLL is valid. – user4574 Mar 16 '23 at 14:34
  • Thanks, I'll look into phase locked loop. – BipedalJoe Mar 16 '23 at 15:44