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If I have a pair of I2C traces (SDA and SCL) on a 1 oz board, each being 8mil wide and separated by an 8mil gap, how long would the traces have to be before crosstalk would become an issue?

Edit:

Apologies for not making this clear before, but I was asking from a theoretical point of view, and with everything else considered equal.

I was checking the rise times on an I2C bus, and the crosstalk spikes were larger than I would have expected (300-400mV). After reading some of the replies, I measured the fall time - it's about 15nS, and from my calculation I must have about 80pF of capacitance on the bus.

PDug
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    In addition to the answers below, it depends on your noise margin. The narrower your input threshold levels the less immunity you have. Also, it depends on your edge rates as Gman mentioned below. The easiest solution is just don't run the traces next to each other.. – Analog Arsonist Apr 18 '13 at 22:26

4 Answers4

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Crosstalk is usually not a problem, when the I2C bus is contained within a single PCB and pull-up resistors are properly sized. As the size of the bus grows, bus capacitance will become a problem before crosstalk becomes a problem.

If you think that capacitance between SDA and SCl is high, run a grounded trace between them.

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(Source)

Nick Alexeev
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While I can't say when issues will happen, in a practical sense, I can tell you what is recommended.

Phillips, the i2c creator, recommends a SDA VDD VSS SCL pinout on cable for that very reason.

The reason for unusual arrangement of the power lines being between the I2C wires is to stop crosstalk. ie the edges of SDA and SCL coupling together. Placing VDD and GND between SDA and SCL, means that the capacitance on either signal line is equal (for 4 wire cable)

This is the Philips recommendation. The pattern is that set out in section 17.3 of The I2C Bus Specification. (There are recommendations for twisted pair as well)

If the length of the bus lines exceeds 10 cm (ribbon cable or on pcbs)
This arrangement will have similar capactive loading on SDA and SCL.
Where you don't use pins 5 & 6, it can be better to just use 4 wires. For longer runs, use twist&flat ribbon, or split 5&6 from 1-4
Avoid bundled cable where the conductors aren't individually twisted pairs or individually screened

Emphasis mine. From the actual Specs (Section 17.3):

These wiring patterns also result in identical capacitive loads for the SDA and SCL lines. The VSS and VDD lines can be omitted if a PCB with a VSS and/or VDD layer is used.

If the bus lines are twisted-pairs, each bus line must be twisted with a VSS return. Alternatively, the SCL line can be twisted with a VSS return, and the SDA line twisted with a VDD return. In the latter case, capacitors must be used to decouple the VDD line to the VSS line at both ends of the twisted pairs.

If the bus lines are shielded (shield connected to VSS), interference will be minimized. However, the shielded cable must have low capacitive coupling between the SDA and SCL lines to minimize crosstalk.

Having a ground plane (or vcc plane) below the traces is enough, according to NXP/Phillips.

Now, to be honest, I currently use a 10 INCH (25 cm) cable, with SDA/SCL twisted together, and separately, VCC and Gnd. Works fine at the 125khz speed I am using, no errors or nacks, and I'm pretty much doing the opposite of what it says I should do. While the 17.3 section does not mention as this being only for 400khz or 1000khz speeds, it seems to be very very cautious.

Passerby
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I'd guess that the traces would have to be parallel for many feet before you'll see significant crosstalk. You could always check this free app and report back to us. :o) http://www.ultracad.com/ct_calc.htm

A couple other things, the worst edge is going to be the falling edge of either SCL or SDA since they are driven by an active n-ch pulldown. But if the chip manufacturer follows the NXP spec, the pulldown is a multi-stage turn on of the n-ch pulldown resulting in a slew rate controlled edge. And it's not likely to be a 5ns transition from hi-to-lo ( and therefore no transmission line effects). I'd worry more about power supply noise jacking up the ground voltage or glitching the Vdd supply down.

gman
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FWIW, I begin to see pretty severe crosstalk (~1V amplitude spikes) with ~2 meter of cable (industrial M8x4 style, 24awg conductors, light twist). VDD=5V, f_sck = 100kHz. The system still functions without any visible errors but it looks like crap on a scope. Series resistance (Rs in the i2c spec) reduces crosstalk.

aaa
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