RGMII use RX CLK as TX CLK

Question

I'm looking into the RGMII interface spec and something is unclear to me. The PHY gives my FPGA a 125 MHz clock in 1 GBit mode. I also have to send out a TX clock at 125 MHz. Is it legal to use the RX clock, as it's coming into the FPGA on the transmit datapath and then forward that clock back to the PHY?

Answer 1

You can in theory use the receive clock for transmit, in what in other contexts is called "loop timing". However this presents significant interworking problems for ethernet, as it lacks any inherent primary-secondary roles for the two ends of a link.

Specifically consider that the phy Rx clock is recovered from the incoming line, which in turn is generated by the phy at the other end of the cable, which is clocked from the far end MAC.

If both ends of the link use loop clocking, then there is no stable clock reference, and the link won't come up.

As such, for reliable interworking, clock loopback is strongly discouraged for ethernet. Much better to use a local reference for Tx.

This is in contrast to systems such as SDH, where it is common to have loop timed edge devices (though even then, they almost always have local reference to support "free running" mode of operation).

Answer 2

That's generally not a good idea. RGMII is designed to be source synchronous, with the clock launched along with the data being sent, using a specific alignment to the data. This prevents issues with clock-loop induced skew.

This is especially true with RGMII which uses DDR clocking. In the FPGA, this is best done on the TX side using an ODDR flop to generate both the clock and DDR data with well controlled skew. Likewise for for RX, where IDDR will use the PHY-supplied clock to demultiplex the DDR data.