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We are evaluating MIC21LV32 from microchip in one of our applications.

For the current sensing we have used 3 mΩ sense resistor (1206, 1 %, 1 W), as these sense resistors have higher ESL+ parasitic inductance in PCB. During testing with R1=R3=100 Ω, No C2, C3, C4, we are seeing large spikes on CSP-CSN nodes.

My question is, for the current sense filter circuit (R1, R3, C2, C3, C4) below,

how can I decide the values of Input filter components (R1, R3, C2, C3, C4) so, that I can get clean voltage across 3 mΩ resistor alone even though ESL present.

Below is the simulated circuit. CSP-CSN_InputFilter_Simulated

Below is the response of the circuit. CSp-CSN_SimulatedCircuitResponse

I have chosen common mode filter values (R1, R3, C3, C4) in schematic, differential mode filter values (R1, R3, C2) randomly.

With same values I have done testing, but I do not see such improvement in the captured waveforms. Simulation to actual HW only difference is AGND & DGND are connected at one place (near thermal pad), I simulation I have shorted it directly.

How can I go systematically to improve the response of the circuit?

Adding capture with both resistors are 100 Ω, no capacitors are mounted. Capture with 100E on both legs, No Cap's

Top waveform is Math - which is CSP-CSN/3mE.

winny
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user19579
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    I don't think you can filter after detecting current through a resistor with significant ESL. But a wild brain cell wonders if you can make R2 one leg of a Wheatstone bridge, and use an RC in another two legs, and sense differentially, to isolate the resistive response of R2? – Neil_UK Mar 03 '23 at 12:05
  • Can't you just ignore the first part of the waveform (aka blanking). – Andy aka Mar 03 '23 at 12:33
  • @Neil_UK Sounds like a clever approach. But blanking is what everyone does as Andy suggests. Another option is to dissipate a bit more heat and limit dI/dt. The biggest question I have though: seems like a shunt is a tiny part of the circuit, so doesn’t the inductance of everything else just swamp it? And then the current will be swamped by that external inductance, and the shunt just faithfully reports what’s up. Before condemning the shunt, measure the current using a quality wideband current probe. Maybe that’s just what the current is! – Kuba hasn't forgotten Monica Mar 03 '23 at 12:40
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    Don't. Fix the problem by minimizing the parasitic inductance. Connect the sense circuit right next to the resistor with a Kelvin connection, so the load current doesn't flow through any of the sense wires. – user253751 Mar 03 '23 at 14:30
  • You can filter just fine. The proof is easily solved: a single-pole RC filter with R*C = L/Rshunt. If you have common mode problems, that's an entirely different problem dependent on your layout, current source and receiver/amplifier. – Tim Williams Mar 03 '23 at 15:04
  • @Andyaka, Tim Williams,Neil_Uk, I am sorry i was late, My family is down with FLU. I will put a capture of the real measurement. I will try to add parasitics between AGND and DGND(one resistor and Inductor). I will post again after that.... – user19579 Mar 09 '23 at 13:28
  • @Neil_UK: Wheatstone bridge idea i didn't clearly understood. How can i isolate the response of R2 using wheatstone bridge? Are you saying what currently i am doing? – user19579 Mar 10 '23 at 11:58
  • @Andyaka : "Can't you just ignore the first part of the waveform (aka blanking)." - The IC takes the csp-csn voltage to decide whether IC is in Current Limit or not? There is no way i can instruct IC to neglect blanking. I can only give IC cleaner signal. – user19579 Mar 10 '23 at 12:00
  • @user253751: IC is in one side of the PCB, sense resistor + other components are on other side. Kelvin routed. Still we can't remove the effects of 1206 Internal inductance. – user19579 Mar 10 '23 at 12:02

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