I was hoping I could get some help with a floating point adder I'm designing in verilog. The test case I am having trouble with is adding the following 2 numbers:
- 37 1.96533143520
Op A: 0x92fb8ffb (1 00100101 11110111000111111111011)
+ 36 1.08916580677
Op B: 0x120b69c9 (0 00100100 00010110110100111001001)
The difference in exponents is 1. So I add the hidden bit back in to both mantissas, shift mantissa B to the right by 1 and add. I do not round because the remainder is exactly half and the LSB of the Mant is 0 (I'm using round to even).
Mant A: 0xfb8ffb (111110111000111111111011)
Mant B: 0x45b4e4 (010001011011010011100100.1) G=1, R=0, S=0
Sum: 0xb5db17 (101101011101101100010111)
The sum is already normalized so I do not do any further modification to the mantissa. I use the sign and exponent of Operand A and the new mantissa sum to provide the result, but I do not get the expected result:
- 37 1.4207485914
Result: 0x92b5db17 (1 00100101 01101011101101100010111)
- 37 1.4207484722
Expected: 0x92b5db16 (1 00100101 01101011101101100010110
Is there someone who can help me understand what is going on? Is the issue that I am supposed to wait until AFTER adding the mantissas to determine whether to round or not? I don't see why this would make a difference.