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I have a D Flip Flop, whose /set line is controlled by an ATmega, and its output (Q) is connected to the /WAIT line of a Z80 processor. Of course, I need that at power on, the Q output is set HIGH to prevent the Z80 from entering in WAIT.

I think that this should be a good solution: at power on, C is discharged, and regardless of the status of WS_DISABLE ( high or low ), the /S is connected to GND.

After the C is charged, the diode D1 will detach this RESET circuit from the /S pin, so that ATmega can operate with no issue using the WS_DISABLE line. In the case of WS_DISABLE high at power on, R2 will limit the current from ATmega.

What do you think? Are there better options?

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ozw1z5rd
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  • The slow raising edge from an R/C combination might not be correct for your flip-flop. I would use a Schmitt-Trigger and a gate to combine both signals. – the busybee Feb 11 '23 at 14:23

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