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Can the output of a D-type latch go metastable when:

  1. There is a minimum CLK/ENable pulse width violation
  2. The input and the output of the latch have the same value?
TonyM
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Viktorinox
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  • A very warm welcome to the site. I'm pretty certain it's a 'no' but I'm afraid I don't have the time to write the decent and substantiated answer this needs. – TonyM Jan 21 '23 at 22:42
  • By latch, do you really mean latch or actually mean a flip-flop? (A latch lets its input flow to its output while its CLK/EN is at one level and holds its value while CLK/EN is at the opposite level. A flip-flop transfers input to output on a CLK edge,) – TonyM Jan 21 '23 at 23:38
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    Any logic block is ideal, and the behaviour how it works under various conditions depends on the implementation. – Justme Jan 21 '23 at 23:43
  • I think OP means a latch, because the basic D-type flip flop does not have an enable. – SteveSh Jan 22 '23 at 01:03
  • @SteveSh, I think so too, but FPGA registers as FFs (eg a DFFE) have CLK and EN. OP: please edit your question to clarify what technology you are considering here and why. – TonyM Jan 22 '23 at 10:47
  • Here I was referring really to D-latch and not D-FF. I'm asking this question because in the lib file of the technology we are using, the latch model is generating X at the output when there is a short pulse on the enable even though Q and D are the same – Viktorinox Jan 22 '23 at 20:20
  • The model will complain of timing violations and signal this with an X, regardless of what the real one will do. Which I imagine you realised. Incidentally, please edit new information into your question rather than adding it in comments. Otherwise, readers have to piece together the full question. – TonyM Jan 23 '23 at 07:32

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