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I am currently building a simulator (time-domain model) that includes a System-on-Chip, a constant voltage source and a series resistor.

Current solution: My initial intuition was to model the SoC's consumption as a constant-power-sink: I attribute each task I expect the SoC to execute a power value and an execution time.

Problem: As I calculate the voltage seen by the SoC I have to take into account the voltage drop across the series resistor. At the next time step, the current is already higher to compensate for the lower input voltage. This continues and especially with high series resistances quickly ends up at voltages close to 0 V and extremely high currents.

Is there a more reasonably way to model an SoC's power consumption?

toolic
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MoTex_42
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    Why constant power? – Bruce Abbott Jan 20 '23 at 11:27
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    Most MCUs will have rather constant current over allowed operational voltage for a given task. – winny Jan 20 '23 at 11:54
  • @winny: You are right; this is what I see in most data sheets. However, when I run some benchmarks on a ARM Cortex-M4-based SoC and measure power consumption while sweeping through the allowed operating voltage range (1.7V - 3.6V) I see that with lower voltage, the power consumption only changes marginally (<20%). With a constant current consumption I would expect half the power when reducing the voltage from 3.4V to 1.7V. That's why I thought that it behaves more like a constant-power-sink. – MoTex_42 Jan 20 '23 at 12:26
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    @MoTex_42 sounds like you have *actually measured* its I/V curve so why not use that actual curve instead of guessing what it kinda looks like? – user253751 Jan 20 '23 at 12:30
  • Thanks for the advice. I could indeed do that but that would require me to characterize each task by an individual I/V curve instead of a single power/current value. But you are right, that would probably yield the most exact results. – MoTex_42 Jan 20 '23 at 12:33
  • You can also work out whether the curve you have measured is a constant power curve or not – user253751 Jan 20 '23 at 13:21
  • I repeated my measurements for 1 benchmark at 3 different voltages: `3.5 V: 3.69 mA, 12.9 mW | 2.5 V: 4.61 mA, 11.54 mW | 1.6 V: 6.83 mA, 10.93 mW` This shows that the SoC behaves much more like a CP-sink, rather than a CC-sink. The problem I see with modeling that is also, that the effect is more extreme the smaller the step size in my simulation. With a 100x smaller step size between calculations, I execute my "feedback loop" 100x more. So what step size would then yield the most realistic results? – MoTex_42 Jan 20 '23 at 14:15

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