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I need to wire up the four GPIO pins (connected to the FPGA pins) in a way that keeps the value of the pin at a pulled up value of appropriate voltage. I have an option to use the pullup resistors. When not sending or receiving data, both modules' respective pair of bidirectional clock/data lines are supposed to remain high until one module begins sending.

Configuration Diagram

Loopback Configuration Diagram

The more I think about this, the more I am split between the options I have presented in the question. My question follows, and describes a module connected to another module bidirectionally as the module were to connect if the other module were an actual input mouse device but rather on the outside of the system (so no loopback would be present at all).

Question

Are pullups needed to create my loopback, do I need to specify them directly via FPGA constrains and remove the pullup resistors (and the 3.3V source), or do I need to just loopback without any pullup configuration?

Vahe
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    Since your intent is to simulate and occasionally validate the design with a real a device talking over open-drain bus which is using pullups by design - yes you need pullups, either external resistors, or internal pullups available in fpga pin buffers. Whether you can get away with weak internal pullups - this depends on the communications speed with the planned device and the electrical capacitance of the wiring. With PS/2 clock frequency around 15kHz clock, and with no lengthy wires between fpga pins you should be totally ok with fpga internal weak pullups, which you must explicitly enable. – Vlad Jan 21 '23 at 10:46

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