Conduction losses calculation of a SiC MOSFET

Question

I have a question regarding conduction losses calculation of a SiC MOSFET. What I found in different research papers and in application notes is that you calculate the power dissipated during forward conduction, reverse conduction, and body diode conduction of the SiC MOSFET, and if you add up all three values you will get the total conduction losses of SiC MOSFET.

This is something weird for me because previously when I was calculating losses for conventional silicon MOSFETs, the loss in the body diode during dead time was always accounted for in the switching losses, not in the conduction losses. Can anyone please explain why it's so?

Answer 1

I think the confusion here (as evidenced by the comments, and probably your confusion as as well) is when and how body diode losses occur.

Very little information about an actual application has been provided, but if we can assume something typical like a half-bridge, with full-wave drive (PWM total near 100%) minus a little dead time, as would be used in a synchronous buck or boost or class D inverter, then the body diode only conducts during dead time.

This requires R_DS(on) to give lower voltage drop than the body diode, so that synchronous switching is being done.

In this case, the body diode only conducts for a fixed time, and thus (at constant load current) dissipates fixed energy. Which means power proportional to F_SW.

Personally, I'm not too concerned about how the loss is classified; the circuit just does whatever it does, regardless of semantics. It would seem that by @tobalt's comment, the above should be switching loss. But you can call it however you like, as long as the total works out correctly.

Perhaps in previous examples you were seeing body diode used for conduction as well, in which case it would contribute elements to both kinds of loss.

Note that body diode recovery loss can be considerable, and dead time creates the worst-case condition of a brief forward-bias that can cause sharp recovery*. Not only increasing switching loss, but device peak voltage and EMI too.

*As forward bias duration is reduced closer to or below t_rr or thereabouts, charges aren't reaching quasi-equilibrium in the junction before reversal, which causes recovery to be not only faster, but much sharper (less softness). My tests of Si MOSFETs have shown this is a small effect for them (not entirely sure why; they have also shown negligible forward recovery effect), but I don't know if that remains true of SiC, or for what types (since it depends on doping, geometry, probably SiC allotropes too).

Particularly for synchronous and class-D amplifier use, I'm a fan of minimizing dead time as much as possible. The hazard is shoot-through, but keep in mind where shoot-through current flows: the switching loop, from +V through both transistors to GND, back through the nearest bypass capacitor(s). This loop has inductance, which limits dI/dt during shoot-through. It's not an automatic death sentence, and it doesn't need to incur massive losses in the process. Indeed, overlap can be designed, making a compromise between gate timing (especially mind the range or variance in propagation delay of drivers and such), and loop inductance and snubber loss. This also has the benefit that, by reducing the dependency on load current, distortion may be improved in class D amplifiers. Unfortunately, this can be difficult, as more than say 10s of ns of overlap becomes untenable (too much inductance is required, increasing losses), and many controllers are designed for fixed built-in dead time of perhaps 50ns to 300 or more.