I have design consisting of several interconnected modules. The TimeQuest complains about timing violations, and it is correct in its complaints. The paths it highlights must be out of the optimization, marked as false paths. The lower level module under consideration has a register, it goes through set of multipliers and other logic, the goes out of the lower level module to top module, muxed, then registered and then connected to the bidirectional pin (the fact that there's a register in top-level module makes difference). TQ wants to mark false path from that register up to the wires looking out of the chip. I want to design .sdc file for lower level module only, constraining from register to the output of this lower level module only, and not farther. The rationale is if I will be using this lower level module in other design I will already have module-specific constraint false-pathing the route from register of the module to its output (and if needed, will put more constraints into upper module .sdc file).
But I can't find a way how to do it. Whatever set_false_path arguments I put, I am unable to select output wires (and logic before them) going out of the lower level module.
Let's say, lower level module has register
reg [5:0] my_register;
the there's some logic and embedded functions, and at the end there's
assign output_wires[7:0] = result_for_my_register[7:0];
and this is declared as port for the module
module my_module (
...
output wire [7:0] output_wires,
...
);
How do I tell Quartus/TQ to false the path from my_register to output_wires within this my_module module?
Update 1: thinking further about the issue I concluded that in this lower level module has unregistered output, the target latching register is located in the top-level module, but I can constrain only between registers. Therefore the task seems to be to constrain the register my_register with the -to option wildcarded. Am I correct?
Like this:
set_false_path -from [get_registers {my_module|my_register[*]}] -to [get_registers {*}]
But this technique seems not correct falsing all the paths from my_register, while I want to false only path going through output_wires... and I am so far unsuccessful with -through clause for the set_false_path...
Update 2:
set_false_path -from [get_registers {my_module|my_register[*]}] -through [get_nets {my_module|output_wires[*]*}] -to [get_registers {*}]
seems to do a job, but I am not sure if the result is appropriate. Please advise.
Update 3: To make false path working within this module I can introduce latching register at the output of this module, therefore module's output will become registered. But I do not need this register spending on its flip-flops and rouing.
