Relationship between PSEL and PENABLE signals in the APB protocol

Question

I would like some clarification on the relationship between the PSEL and PENABLE signals in the APB Protocol. The specification states:

The PENABLE signal is asserted the following clock after PSEL is asserted and de-asserted after a transfer occurs.

I would like to understand the following conditions:

1. Can PENABLE toggle while PSEL is de-asserted?
2. Can PENABLE be asserted in the IDLE and/or SETUP phase?
3. Can PSEL go low in to the SETUP phase?
4. What happens when PSEL is asserted high in the ACCESS phase and PENABLE is not de-asserted?

Please refer to the link: https://www.eecs.umich.edu/courses/eecs373/readings/IHI0024C_amba_apb_protocol_spec.pdf

Answer 1

Consider an APB configuration with one master and 2 slaves, where the PENABLE signal (driven by the master) is common to both slaves and the 2 PSELx signals (driven by the master) are one-hot encoded (only one of the PSELx signals can be 1 at any given time).

PENABLE can toggle while PSEL is de-asserted. For example, if the master addresses slave2, then slave2's PSEL=1, and slave1's PSEL=0. Since slave1 is not being addressed, its PENABLE is ignored.

PENABLE can be asserted in the IDLE state. Refer to the previous explanation.

PENABLE should not be asserted in the SETUP phase of an addressed slave because that would violate the specification which you quoted above.

PSEL should not go low into the SETUP phase since that would prematurely terminate a transfer.

If PSEL is asserted high in the ACCESS phase and PENABLE is not de-asserted (PSEL=1 and PENABLE=1), that is a normal situation for the ACCESS phase.