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I know it is a very basic question but I couldn't really find an answer on the internet. Our lecturer told us it is used to reduce the number of transistors used in the design.

Our first case without an inverter at the end (AND gate):

Without an inverter

This is the second design with an inverter (AND gate):

With Inverter

In the first design we used 4 gates, in the second it was 6, so how does this reduce the number of transistors used?

ocrdu
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Neverhadagf
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  • There is building a circuit from discrete components, and there is fabricating an integrated circuit. Please add to the body of your question which it is to be about. In case of ICs: How are both polarities included in a single chip? – greybeard Jan 11 '23 at 12:07
  • (Note that in both cases, there are two "implied inverters" in the negated inputs (gates with squiggle).) – greybeard Jan 11 '23 at 12:12
  • Does this answer your question? [nMOS passing 1's poorly and pMOS passing 0's poorly](https://electronics.stackexchange.com/questions/98390/nmos-passing-1s-poorly-and-pmos-passing-0s-poorly) – Dave Tweed Jan 11 '23 at 12:29
  • Your first design doesn't really work. Think about how the MOS knows whether to turn on or off. Gate voltage, right? But voltage is measured between two points. What is the second point? – user253751 Jan 11 '23 at 13:17

2 Answers2

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The NAND gate implementation you show is not the one with the least number of transistors. It's possible to create a NAND gate with 2 nmos and 2pmos (see wikipedia).

We prefer this NAND gate over the four-transistor implementation of the AND gate because it helps prevent latch-ups. This question also lists some infos about why we want pmos in the pull-up and nmos in the pull-down network.

mlx11
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  • The first diagram is not a NAND gate. It is a (very bad) AND gate. The second diagram does include a NAND gate, but it uses 4 transistors just as you propose. – The Photon Jan 11 '23 at 15:48
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    How does the AND gate implementation increase the risk of latch-up? This makes no sense to me. – Elliot Alderson Jan 11 '23 at 18:51
  • To the best of my knowledge using nmos for the pull-down and pmos for the pull-up ensures that the junctions are not forward biased which reduces the risk of latch-ups. – mlx11 Jan 12 '23 at 20:13
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The four-FET ‘AND’ you show in your first diagram doesn’t provide proper gate bias for the FETs to switch correctly. It doesn’t really work.

More here: Why are the voltages the way they are in this transistor circuit?

The second diagram, a NAND followed by an inverter, is standard: n-FETs used in the pull-down network and p-FETs in the pull-up.

I think this question comes from a misunderstanding of how FETs actually work, a detail that a typical logic-FET diagram like yours (bubble on gate for p-FET, no bubble for n-FET) tends to obscure.

What's not shown in either diagram is the source substrate connection. FETs turn on based on their gate-to-substrate voltage.

In the second (working) diagram then, the substrates connected as follows:

  • n-FET source substrate is connected to GND or other low
  • p-FET source substrate is connected to Vdd or other high

Following this rule ensures that the gate-source (substrate) voltages applied to the FETs are driving them fully on or fully off. Then you get the switch-like behavior you expect: logic '1' turns on the n-FET, logic 0 turns on the p-FET.

hacktastical
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