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The eval board for the GaN half bridge module LMG5200 (datasheet) contains the following circuit to generate dead time from a single PWM input.

enter image description here

The half-bridge module itself has good propagation delay matching (2 ns) and fast switching (few ns). Therefore, the eval board advertises that a short 7.7 ns dead time is sufficient.

My question is, isn't this circuit unsuitable to generate the dead time for such a fast half-bridge? Wouldn't the dead time be strongly different between the UP/DOWN transitions? Because the LO_SIGNAL branch contains one additional LVC inverter (U3C) with a propagation delay of nominally 5.4 ns.

Is this skew somehow compensated? If not what could be used as a more symmetric dead-time generation circuit from a single PWM input? One version I have found mentioned a lot uses a delay and two gates (AND, NOR) (example from Andy). But I wonder, if it is appropriate for ~ns delay matching because it uses two different gates.

winny
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tobalt
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1 Answers1

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Schmitt tirgger devices such as U3 in your schematic have fast switching times, but also have two fixed thresholds. They trigger at a higher threshold on a rising edge, and a lower threshold on a falling edge as shown in this image from https://components101.com/articles/schmitt-trigger-introduction-working-applications . What is important is the fixed threshold acts like an analog comparator in this circuit.

enter image description here

The typical switching time of a lightly loaded inverter is probably one or two nanoseconds for these devices; this is not how you are setting your dead time. Instead, you are slowing the fall times on C22 and C35. On the rising output of U3A or U3C, D3 and D4 are forward biased and every thing switches quickly. But when R2 or R14 are pulled down, the fast-switching diodes D3 and D4 are back-biased so the capacitors must be discharged through the resistors, and this switching does not occur until the lower threshold (Vt- in the figure) is reached. So, when U3A output is on the rising edge U4B switches immediately, but U3C output is on the falling edge and U4A's switch is delayed while C22 is discharged down to Vt- through R14. And vice versa. The difference between these two switching times is the dead time. Adjusting the RC values will result in increasing or decreasing the dead time.

John Birckhead
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  • I am aware of this... But the question is about the ***additional*** propagation delay of specifically `U3C` which doesn't exist in the lower branch. The RC delay time constant is ~4 ns, which is on the same order of magnitude as the additional `U3C` delay. Therefore, wouldn't the dead times be different by the LVC prop delay between the UP/DOWN PWM transitions ? – tobalt Jan 09 '23 at 14:27
  • You're right of course that there is one more gate in one path than another, so you will have some difference in dead times between the two states. The propagation delay at Vcc = 5 volts is listed between 1.5 and 4.7 nsec. And, if you take a look at figure 1 in your data sheet for U3, and you can see that the propagation delays are measured under relatively heavy loads. I think the added gate delay would not be a major factor, but it might be good to measure your dead times just to be sure, and to take care in your layout if you use this circuit. – John Birckhead Jan 09 '23 at 14:47