I am trying to implement ECDSA signature verification algorithm. I am facing errors in the synthesis part

Question

I wrote a synthesizable Verilog HDL code in Xilinx Vivado to implement ECDSA Signature Verification. There are no syntax errors, but synthesis failed. The inputs I am taking are of 7 bits each - r,s,P,Q. I have left out the hashing part(instead I explicitly tried declaring the 32 bit hashed value e, where e = H(m), m being the message of 32 bits.). Still there are errors while synthesis. I have listed out the errors after the code. There are no output bits from this module, so will the Vivado truncate the code? If yes, how should I resolve it?

`timescale 1ns/1ps
module signature_verification(r,s,P,Q);
parameter n = 80;//n is declared to be 80
integer i;
input wire [6:0]r;
input wire [6:0]s;
input wire [6:0]P;
input wire [6:0]Q;
reg e[31:0];

//creating array of elements 1 to n-1
integer verify_array[0:78];
initial
begin
    for(i=0 ;i<79;i = i+1)
        verify_array[i] = i+1;
end
//check whether r and s integers fall in the array of elements 1 to n-1
initial
begin
    for(i=0;i<=80;i = i+1)
        begin
        if(r[i]!=verify_array[i])//recheck
            begin
            if(s[i]!=verify_array[i])
                $display("Reject the signature.");
            end
        end
end


//e = H(m) left out
//for the time being skipping the hashing part
e <= 32'b10000000000111000000000001111111

//finding modular inverse of s
function [6:0]w;
input [6:0]s;
input [6:0]p;
integer i;
begin
    for(i=1;i<p;i=i+1)
        begin
        if(((s%80)*(i%80))%80 == 1)
            begin
            w[i] = i;
            end
        end
end
endfunction

//------------------------------------------
//computing u1 and u2
reg [6:0]u1; 
initial
begin
for(i=0;i<7;i=i+1)
begin
u1[i] <= ((e[i]*w[i])%n);
end
end

reg [6:0]u2; 
initial
begin
    for(i=0;i<7;i=i+1)
    begin
    u2[i] <= ((r[i]*w[i])%n);
    end
end


reg [6:0]X;
reg [6:0]X_int;
initial
begin
    for(i=0;i<7;i=i+1)
    begin
    X[i] <= ((u1[i]*P[i])+(u2[i]*Q[i]));
    end
end

//converting X to v
reg [6:0]v; 
initial
begin
    for(i=0;i<7;i=i+1)
    begin
    X_int[i] = int(X[i]);
    v[i] <= (X_int[i]%n);
    end
end

//checking if v=r
initial
begin
    for(i=0;i<=80;i = i+1)
    begin
    if(r[i]!=X_int[i])//recheck
        begin
        if(r[i]!=X_int[i])
            $display("Reject the signature.");
        end
    end
end
endmodule

Here I have to check whether X is approaching Infinity. How can I do that in Verilog HDL, since it is a hardware description language unbounded elements cannot be checked?

Answer 1

I am not sure if I got your questions correctly. Please try to be more specific about the question and post the errors. However, I will try my best to answer as much as I understand. Point to be noted, I am also a newbie to vivado/FPGA development. Dear experts, Please be kind enough to correct me if my answers seem wrong to you.

1. The good practice for Verilog to be "synthesized" is to use an output port to my knowledge. Let's say done=1 when signature generation is done. My best guess is if there is no output port, vivado shouldn't give you an output for "synthesis". Imagine you are trying to build a circuit that takes input but doesn't generate any output. I believe vivado optimization will not find a solution to generate a synthesizable circuit. To my understanding and knowledge, the circuit doesn't make sense at all. There might be special cases where this might be applicable, which I haven't seen so far anywhere tbh.
2. For unbounded elements, my best guess would be to use a large enough number as a reference of infinity which will indicate that X is approaching infinity. You can also switch to the system Verilog. I believe there might be instances where you can use unbounded checking.