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I'm interested to know if there are real-world measurement values available for the resistance contribution of vias (or plated through holes).

Sure - there is no widespread definition of what a standard PCB actually is.

To make the an answer useful not just for me imagine your preferred PCB manufacturer with it's default design parameters would provide the PCB (one of mine would be multi-cb for instance).

Anyway, let's make the following assumptions:

  • standard FR4 2-layer PCB with 35µm of copper (1 ounce per square foot), maybe 1 square inch in size
  • the via in question connects the two copper planes in the centre so the resistance of the plane is low compared to the via
  • by depth of via I understand the thickness of the base material, which such as (1.5, 0.8, 0.5) mm
  • the diameter of the via varies such as (0.2, 0.25, 0.3, 0.4, 0.5, 0.7, 1.0, 1.5, 2.0) mm

The question came up while pondering more and more often about optimization possibilities of space-sensitive PCBs in the environment of charging and protection circuits of Li-ion batteries, especially when considering how many stitching vias with which diameter would be the best choice in terms of lowest resistance and also lowest board area.

If a universal answer can be found, it could certainly be useful to many aspiring PCB designers.

Although my question is primarily about DC resistance, I'm not sad if the answer happens to describe the impedance contribution of vias.

Edit: replaced "PTH" with "via" everywhere

datenheim
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  • This is a DC question, correct? You have everything you need, current, copper, temp-rise, dimensions & math. Get to it... If it's a high frequency (or fast rise-time) question, then more specs are needed. – Chris Knudsen Dec 23 '22 at 20:13
  • Yes, it's more a DC question, maybe extendet for inductance. I know how to calculate it in principle with more or less inaccurate simplifications. But I suspect real-world PCB will have more influences as I know and therefore ask for messured data. We could compare those with calculated values later... – datenheim Dec 23 '22 at 20:44
  • In [his answer](https://electronics.stackexchange.com/a/647458/326463) @Bruce Abbott contributed rough measured values for 0.33mm via of 0.5 mΩ and 1.0mm via of 0.1 mΩ on a 1.6mm 1oz board. – datenheim Dec 24 '22 at 12:12
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    I suspect a more detailed answer (beyond copper plating weight vs via length) is going to depend on intricate details of how your specific factory plates through holes and how uniform that copper layer ends up. – user1850479 Dec 24 '22 at 15:53
  • I hope to collect enough responses to finally assemble a table of via resistance vs. via diameter and via depth, each with calculated and reported min-average-max values from multiple manufacturers to gain wider understanding of via resistance in general. – datenheim Dec 25 '22 at 11:10
  • Today I got feedback from a PCB maker. Plating width of vias does not depend on via diameter and via depth. For 35µm copper on outer layer they state 18...24 µm of via plating as standard. The plating thickness in vias DOES NOT increase for thicker copper, no matter if 70 µm or 105 µm! With outer copper layers of only 18 µm the plating thickness of vias DECREASES to around 12 µm mean (maybe 10...15 µm range). Both has serious implications for getting larger currents through vias. I was explicitly warned that even with 105 µm outer copper the vias are the underestimated weaknesses. – datenheim Jan 02 '23 at 19:08

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