Question about the Verilog-A implementation of a VCO

Question

I am learning verilog-A to model analog circuits. One of the examples given in the book is that of a voltage-controlled oscillator (VCO).

The book says the following about how the VCO can be modelled (see image).

I am a little bit confused over why they decided to integrate the frequency and not just use something like:

$$ f_{\text{out}} = f_{\min} + \left( \frac{f_{\max} - f_{\min}}{v_{\max} - v_{\min}} \right) (v_{\text{in}} - v_{\min})$$

$$ v_{\text{out}} = A \cdot \sin (\theta) = A \cdot \sin (2 \pi \cdot f_{\text{out}} \cdot t + \varphi) $$

module vco0 (out, in);

input in; voltage in;                           // input terminal
output out; voltage out;                        // output terminal
parameter real vmin=0;                          // input voltage that corresponds to minimum output frequency
parameter real vmax=vmin+1 from (vmin:inf);     // input voltage that corresponds to maximum output frequency
parameter real fmin=1 from (0:inf);             // minimum output frequency
parameter real fmax=2*fmin from (fmin:inf);     // maximum output frequency
parameter real va=1;                            // amplitude
real freq, phase;
integer n;

analog begin
    // compute the freq from the input voltage
    freq = (V(in) - vmin)*(fmax - fmin) / (vmax - vmin) + fmin;

    // bound the frequency (this is optional)
    if (freq > fmax) freq = fmax;
    if (freq < fmin) freq = fmin;

    // bound the time step to assure no cycles are skipped
    $bound_step(0.2/freq);

    // phase is the integral of the freq modulo 2 pi
    phase = 2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);

    V(out) <+ va*sin(phase);
end
endmodule

score 1 · Answer 1 · answered Dec 18 '22 at 12:53

The integral is required because that's pretty much the definition of any oscillator: Frequency is the derivative of phase, and phase is the integral of frequency.

Phase is the key value in a time-domain simulation, because it tells you where each cycle of the output begins and ends.

Your proposed formulation is one way to do the integration, but it makes the assumption that the frequency has been constant for all time from the start of the simulation until the current time. Obviously, if you're dealing with a VCO, you're expecting the frequency to vary with time, so you need to do the actual step-by-step integration as the simulation proceeds.

Question about the Verilog-A implementation of a VCO

1 Answers1