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I need some expert advice and I trust I can get it here. I am in the process of designing a system that uses a PDM microphone connected to the the microcontroller via a flexible PCB (4.8 MHz clock with obviously much faster slew rate for rising and falling edges, only clock signal is shown to simplify problem).

My intention is to route both PCBs 50 Ω impedance traces (single ended). The rigid board is pretty straight forward to get the impedance correct with online calculators however the flexible PCB is turning out to be a bit of a headache. I have submitted the design to PCBWay with the intention of having a 0.1 mm thickness (can vary), impedance controlled option checked and also including EMI shielding as this has to get FCC certified.

Stack up currently is ground plane, dielectric, signal layer, EMI shield. Initially when we spoke to them they said we can stack 4x0.25 mm of the Pi (polyimide?) which requires a track width of 0.214 mm which I'm quite happy with. They later said they cannot do x4 dielectric stack up and the trace width need to be 0.05 mm (2 mils) which is an incredibly thin trace, I really want to go thicker.

I need suggestions here? Do I change my charactistic impedance on the flexible PCB or how do I change the stack up to get a wider track? Or do I just go with the 0.05 mm trace width?

p.s. Is my termination resistor of 50 Ω or less correct at the source, since it absorbs the reflected wave?

enter image description here

winny
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Ne3M
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    4.8 MHz across 70mm is less than one degree of phase angle, that should be okay to treat as a lumped element. – Simon Richter Dec 05 '22 at 16:44
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    I think the rising and falling edges are more the problem here, I'm just thumb sucking here but if we have fast rise/fall times like 1ns it could be considered a 250MHz signal. – Ne3M Dec 05 '22 at 17:06
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    In that case, add a series resistor at the driver to increase the transition time. – The Photon Dec 05 '22 at 18:29
  • If the clock were sinusoidal, it would be fine. If it is square with 250MHz components, then it will be less-square coming out, and some of the HF component will be radiated as EMI. Will the PDM accept a sinusoidal clock? – rdtsc Dec 05 '22 at 18:29
  • I don't see a reason why it won't accept a sinusoidal, just trying to get the characteristic impedance of the flexi pcb correct. – Ne3M Dec 05 '22 at 18:48
  • 250 MHz is almost two decades out, those harmonics are more than 30 dB down. – Simon Richter Dec 05 '22 at 18:54
  • Have you tried Saturn PCB calculator? Your case seems complex, but it’s free so worth a try? – winny Dec 05 '22 at 21:08
  • There is nothing magical about 50 ohms for a trace impedance (unless you're talking about RF matching, which is usually targeted to 50 ohms). 30 ohms, 40 ohms, 50 ohms, 60 ohms - it makes little difference in the digital world (even at high speeds), so long as 1) impedances are matched all along the interconnect; 2) the driver can source the current needed; and 3) the destination has the proper termination. – SteveSh Dec 05 '22 at 21:52
  • The stack up on flexi PCBs are not as easy getting it right for 50 Ohm. I just wanted to use 50 Ohm since it is the industry standard, getting to 50 Ohm requires a trace width of 2 mil which is insanely thin, different dielectrics does not solve the problem. Since 50 Ohm is the industry standard I didn't think it would be a problem, hence me asking for stack up solutions. The problem is that the Rigid FR4 has already been produced at 50 Ohm, I'm now leaning towards adjusting the characteristic impedance of the rigid FR4 board to match the impedance on the flexi PCB. – Ne3M Dec 07 '22 at 13:04
  • When you say the stackup is "ground plane, dielectric, signal layer, EMI shield", are you talking about the flex? – SteveSh Dec 07 '22 at 14:43
  • A cross section sketch of your stackup & layers would be helpful, for both the rigid and the flex parts of your design. – SteveSh Dec 07 '22 at 14:44

3 Answers3

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Your and @Simon_Richter's comments are key here, on principles at least. The amount is all that's the matter.

To clarify the relevant amounts, then:

The fundamental wavelength is unimportant; edge rates matter.

The electrical length of the rising edge, even from a fast MCU of ~1ns (~20cm), is relevant to signal quality purposes. It is still insignificant over this length (7cm, assuming a straight-line route).

The short length, means the trace can be modeled as a simple L, C, LC or R element; which one, depends on its impedance relative to its termination(s).

In this case, due to dielectric thickness and available trace widths, and the high impedance load (assuming it's a CMOS input pin), it seems likely the trace will have a lowish impedance, so it will manifest as C.

You have the option of using a minimum source impedance equal to the CMOS pin driver impedance (typically ballpark 40-70Ω), or higher (by adding external source termination). A higher resistance gives an effective R-C low-pass circuit. You could also use series inductance to make a 2nd order low-pass, or in general, any filter network between driving pin and trace.

If slower edges are tolerable, the lowpass effect can be valuable to reduce harmonics. How far, depends on the acceptable rise time. There should be a maximum risetime specified on the device. (This spec also likely restricts the device from using a sinusoidal input, by the way.)

You may not need the EMI shield, particularly if the harmonics are reduced with excess source termination. The signal can also be filtered explicitly (with an RLC filter section), to attenuate harmonics even faster. It seems unlikely this would be necessary.

Note that the same logic applies to the PDM returned from the device: it should be source terminated or filtered to about the same degree as the clock. PDM has few edges/sec. than the clock driving it, so it will be less critical with respect to RFI (by ~6dB).

As for harmonic content, 250MHz may be -34dB from the 4.8MHz fundamental, but that's still ~50mV peak, and EMI limits are closer to single digit mV. Now, this trace, and the flex extension itself, will behave as an electrically-short antenna, so will have less than unity gain (in the sense of V input → V/m field strength, ignoring antenna factor and other considerations for sake of simplicity). Gain is further reduced by the wide ground and poor coupling off a microstrip trace. It may be that no additional filtering is required, that the antenna gain is less than -34dB to begin with; if it turns out it's higher than this, then somewhere between 0 and 34dB of filter attenuation would be in the right ballpark to deal with it. This could require a high order LC filter to achieve such attenuation, while still respecting risetime requirements; most likely the shield would be preferable at that point.

Most likely, other elements in the circuit will be more prone to EMI, particularly any connectors, or any sections operating on higher voltages and currents (e.g. switching regulators).

Tim Williams
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  • Thank you for this insightful answer. – Ne3M Dec 06 '22 at 11:19
  • Please explain how you got to -34dB for the 250MHz harmonic? – Ne3M Dec 07 '22 at 13:32
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    @Ne3M 250/4.8 ~= 52. An ideal 50% square wave will not have even harmonics, but real waves are rarely perfect, and a duty error of 2% is enough to bring even harmonics up by here. Harmonic amplitudes go as 1/N so the harmonics here will be 1/50th voltage. 1/100th would be -40dB, but this is half or +6dB so -34dB. To be exact, \$20 \log \frac{4.8}{250} = -34.33\ldots\$ – Tim Williams Dec 07 '22 at 15:25
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    We're picking 250MHz because it's the knee corresponding to risetime; for an ideal trapezoid wave (i.e. square with slanted sides), harmonics change from 1/N to 1/N^2 at the corresponding point. Real square waves are rounded too, so there will be additional cutoffs at some point. And also peaks due to ringing and etc. So, using 1/N up to the risetime equivalent frequency is justified. – Tim Williams Dec 07 '22 at 15:28
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From my own experience, after you build the boards and are testing in the lab, or when doing EMI testing, its useful to have adjustment points to adjust the source impedance of the driver or the rise time of the clock edges.

At a minimum you are probably going to want to put an RC filter on each clock and data line at its source. For a 4.8MHz signal I would start with 33 ohms / 100pF and adjust from there.

This setup will allow you to adjust both your source impedance and rise time. And will filter out a lot of the higher frequency harmonics.

schematic

simulate this circuit – Schematic created using CircuitLab

I am not sure how cost sensitive your design is, but it seems like an extra two cents worth of parts on each data line is worth not failing your FCC tests. If it turns out that there is enough parasitic capacitance that you don't need to add extra, then you can always mark it as do-not-populate in the design files and drawings.

user4574
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    I usually pick the R&C values based on a Hyperlynx simulation of the interface, where you can run corner cases (like fast-strong) quickly. – SteveSh Dec 06 '22 at 01:11
  • @SteveSh Using simulation is a good strategy so long as the models are accurate. I generally agree with doing it when you have access to those expensive tools. – user4574 Dec 06 '22 at 08:13
  • Well, building and the measuring only gives you one data point, unless you're going to do that over temperature, supply voltages and parts from different lots. – SteveSh Dec 06 '22 at 12:37
  • I will change the design to implement this. Thank you. – Ne3M Dec 07 '22 at 13:34
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Designs usually don't need to consider transmission line effects until after 50 MHz.

If the board house can't give you board stackup information on the 50 Ω traces, you should be able to calculate the width of the single ended trace with a calculator. You will need to get the dielectric constant from the material.

Tim Williams
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Voltage Spike
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