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While going through DDR3 and DDR4, there is a term called vref. Where in DDR3 it is outside the DDR and for DDR4 it is inside the chip. Why we need training for it. What is the use of it.

Selva97
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\$V_{ref}\$ is the comparison voltage to determine whether a data line is at high or low state.

For DDR3, this is half of the supply voltage for the drivers that drive these lines (so the I/O supply), this can be generated easily with a resistor divider, and reused after buffering as the termination supply for the A/C lines.

For DDR4, the lines are driven asymmetrically, so the center of the data eye is not at half voltage, and in fact slightly different for each IC, so RAM ICs generate their own reference voltage, for this to work a specific training sequence is sent by the memory controller, and the IC determines the optimum reference voltage. This might need to be repeated later as voltages shift due to temperature changes.

Simon Richter
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  • Thanks, but why we go to this feature called vref to check the received voltage is high or low, we can simply confirm it high or low based on DC threshold values like other signals. – Selva97 Jun 07 '23 at 06:31
  • @Selva97, input buffers pretty much always compare against a reference voltage, but many ICs generate this internally with a simple resistor divider, as it doesn't need to be particularly precise. – Simon Richter Jun 07 '23 at 06:41
  • Thanks simon, i got some idea now. Will this vref is constant for all the signals in ddr or each ddr signal can have its own vref for better efficiency. – Selva97 Jun 07 '23 at 09:28
  • @Selva97, for DDR3: each IC has two Vref inputs, one for the Address/Control bus, one for the Data lines. Typical setups will use the same voltage here, but for some power saving modes you might want them separate. For DDR4: it's undefined, the individual ICs generate that internally. – Simon Richter Jun 07 '23 at 10:13
  • Thanks Simon, get overall idea about VREF. Could you please share any useful documents about ddr. – Selva97 Jun 07 '23 at 12:22