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I had a RISC-V CPU with L1 Instruction Cache and L1 Data Cache, and I want to connect these two L1 Caches to unified L2 Cache. I have the following questions:

  1. Does the unified L2 Cache have dual port (one for L1I another for L2D) or single port?
  2. If the unified L2 Cache is single port, are there any specific protocols (e.g. AMBA AXI4) for the cache connection?
  3. How state-of-the-art processors solve this problem?

My current solution is using single port L2 Cache, and connect both L1 Cache to a buffer queue input with cross-bar interconnect. Finally, the buffer queue output connect to L2 Cache.

Multiprocessor Cache Hierarchy

Johnson_NCKU_EE
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    So many options - you’ll probably want to be more specific as to what cache IP you are using. As well, you need to evaluate the system performance in order to make a decision. For all we know your cpu could be clocked at 1MHz which would not require a cache at all. – Kartman Dec 02 '22 at 07:51
  • Please edit the question to limit it to a specific problem with enough detail to identify an adequate answer. – Community Dec 02 '22 at 10:53
  • Depends on the specific cache. I'd guess (since that's what the diagram shows) single-port with an arbiter – user253751 Jan 13 '23 at 14:43

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