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I have a DC voltage with a high ripple current at 10 kHz which produces an audible noise from the MLCCs on the PCB. I can't change the frequency and I need to stick to MLCC class II capacitors for different reasons.

In this article, they say MLCCs mounted at the same place but on different sides of the PCB tend to cancel each other out. Is the same also true if the polarity of adjacent MLCCs would be reversed?

More specifically, assume I have different layouts where many MLCCs are placed close to each other, all connected to + and - of the DC-voltage:

      Layout 1               Layout 2               Layout 3
[+-] [-+] [+-] [-+]    [+-] [-+] [+-] [-+]    [+-] [+-] [+-] [+-]
[-+] [+-] [-+] [+-]    [+-] [-+] [+-] [-+]    [-+] [-+] [-+] [-+]
[+-] [-+] [+-] [-+]    [+-] [-+] [+-] [-+]    [+-] [+-] [+-] [+-]
[-+] [+-] [-+] [+-]    [+-] [-+] [+-] [-+]    [-+] [-+] [-+] [-+]

Assume 1206 capacitors placed as close to each other as possible, e.g. the wavelength of the 10 kHz is large (34 mm) in comparison to the distance between MLCCs.

Would the vibrational waves cancel each other in some layout and thus produce less audible noise over the others? If so, which layout is best for minimising noise?

JRE
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Manne Tallmarken
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  • Layout 1 and 3 seem like they would be rather complicated to route traces to; all the vias necessary would likely require spreading the capacitors out more than you'd probably like. Layout 2 would be easy to route with interdigitated traces. – Hearth Nov 29 '22 at 14:28
  • Yes, layout 2 is indeed much easier to route and that is the layout I am currently using. However, I'm interested in knowing whether changing layout to one of the other two would have any impact on noise. – Manne Tallmarken Nov 29 '22 at 15:14

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