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I am unsure if I am framing the question correctly, but here's what I wanted to ask.

Let's say we want to implement a 64 kB memory. We would require a 16-bit address if we have byte-addressable memory.

One simple way would be to use a complete 64 kB block. Another approach would be to use four blocks of 16 kB each and the lower 14 bits of the 16-bit address and feed it into each memory block, and use the higher-order 2 bits to select which memory block this address points to. This implementation is fairly simple.

But what would happen if we had memory blocks of variable sizes? Say, we have four 4 kB memory blocks, two 8 kB memory blocks, and two 16 kB memory blocks.

How would we have an implementation, as I mentioned above? I don't see any practical benefits of this approach. I just wanted to ask if and how this can be implemented.

ocrdu
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Vedanta Mohapatra
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  • Two 8192 blocks can be achieved with 14 bits for instance. Maybe I'm not seeing your issue? – Andy aka Nov 20 '22 at 12:25
  • In your first example, just think of a single 16 kB block as two 8 kB subblocks which use an extra bit for selection. Then, one of those 8 kB block is itself subdivided into 2 x 4 kB using the next bit. – Nicolas Nov 20 '22 at 12:38
  • Yes it's just a simple extension of your simple approach. –  Nov 20 '22 at 12:50
  • Do you mean RAM or Flash memory? But it does not really matter. You can mix and match any size blocks to implement any total size, as long as the address decoding for it works. – Justme Nov 20 '22 at 12:52
  • @Nicolas Yeah, I think it was a brain fade moment for me. I wanted to ask about any variable-size block. I example I gave really simplified the problem. – Vedanta Mohapatra Nov 20 '22 at 13:12
  • Note that the logic used to select the chips will slightly slow the operation of the RAM bank. You can avoid this by using all the chips at once, as is done on standard DDR DIMMs--each RAM chip holds only one bit of data, and eight of them together make up a byte. (or two bits each, four chips per byte, etc.) This of course is only a concern when trying to push the most performance you can get out of it. – Hearth Nov 20 '22 at 16:47
  • @Hearth Sounds like it would be far more complex if you also want to mix the size of each chip (and if you don't, then you've changed the question) – pipe Nov 21 '22 at 02:21
  • @pipe That was the point I wanted to make, yes. You would have to be careful to match the propagation delay to each chip. – Hearth Nov 21 '22 at 14:53

1 Answers1

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Since all your memory blocks are powers of 2 in size, implementing it is still straightforward.

Your first example (1 block of 64 KB) requires no address decoding. Your second example (4 blocks of 16 KB) requires some address decoding, as you've mentioned.

Your third example just requires more address decoding.

As you mentioned, you need a 16-bit address for the full 64 KB memory. It is common to represent that as A[15:0], where A[15] is the MSB.

You would directly connect the lower 14 MSB's to the 14-bit address input of each 16 KB block: A[13:0]. For the 8 KB blocks, you would similarly connect the lower 13 MSB's to the 13-bit address: A[12:0]. For the 4 KB blocks, you would connect the lower 12 MSB's to the 12-bit address: A[11:0].

The chip-select input for the 1st 16 KB block would be an address decode of the 2 MSB's. The 1st block is selected when A[15:14]=0. The 2nd block, when A[15:14]=1.

The 2 8 KB blocks are selected when A[15:14]=2: the 1st 8 KB when A[13]=0, and the 2nd 8 KB when A[13]=1.

And so on.

SteveSh
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toolic
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