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I have a 3.3 V LDO that I don't want to use for more than ~200 mA. I need 600 mA.

I know that just putting them in parallel is a bad idea. Using op-amps and some sense/shunt resistors, I made ideal diodes to parallel them instead.

I've presented it below. Even accounting for the 2% difference in output voltages between the LDOs, the simulation works just fine: if the load is low (100 mA) it's all handled by one of the LDOs, and if it is high (600 mA) they all work roughly in parallel, to within 5% or so.

What problems am I going to encounter if I try this in real life?

Simulation

ocrdu
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Helpful
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  • Why not just do the standard PNP regulator boost circuit? Your diodes prevent the gate from discharging, and I would be surprised if you get good current sharing out of this. – Hearth Nov 19 '22 at 06:03
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    Which LDOs are you using? – Bruce Abbott Nov 19 '22 at 06:14
  • @Hearth I should have specified: In the diagram above, the output of the LDO is the voltage source. – Helpful Nov 19 '22 at 06:52
  • @BruceAbbott I'm planning on these right now. https://jlcpcb.com/partdetail/86406-ME6210A33PG/C85233 They can handle more than 200mA, but the thermal envelope is my limiting factor and I'm derating quite a bit. Even if this specific application might be better solved another way, I'm still curious about this question. – Helpful Nov 19 '22 at 06:53
  • @Hearth I just registered what it was you were asking, sorry - rather late here. My understanding is that PNP modification requires extra voltage drop, and I don't have it: my power might be coming from a battery as low as 3.5V, so I'm already pushing it with voltage headroom just to use the LDO. – Helpful Nov 19 '22 at 06:57
  • A saturated PNP can have a voltage drop of 100 mV or less, and a PMOS device could have even less at 600 mA. Why not go that route? – PStechPaul Nov 19 '22 at 07:40
  • @PStechPaul Can you give an example circuit? It’s possible I’ve misunderstood other things I’ve been reading… – Helpful Nov 19 '22 at 08:21
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    [This circuit](https://electronics.stackexchange.com/a/552530/29811) controls the LDOs directly and uses fewer components. – CL. Nov 19 '22 at 09:18
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    @PStechPaul: The standard PNP boost circuit requires a B-E diode drop between the unregulated voltage source and the input of the LDO. The PNP is **not** saturated. – Dave Tweed Nov 19 '22 at 12:10
  • @CL. I actually like that idea quite a bit, is there a way to generalize that to more than 2 regulators if I want to parallel more? Also I haven't found any low-quiescent adjustable LDO's (though I recognize I didn't specify that in the question). – Helpful Nov 19 '22 at 19:50
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    You can just add more LDOs, with one opamp per additional LDO. But this circuit works with fixed-output LDOs only if the additional LDOs are lower-voltage models (otherwise, the opamp would need to pull its output below ground.) If you change LDOs, it might be easier to use a low-Iq LDO that supports 600 mA to begin with. – CL. Nov 20 '22 at 11:53

2 Answers2

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the simulation works just fine... What problems am I going to encounter if I try this in real life?

Your simulation doesn't use real-world components, so it's only 'working' by pure luck.

The most obvious problem is no pull-down resistors on the FET Gates to turn them on. I guess some small leakage through the diodes performs this function in the simulation, but that would cause the FETs to turn on very slowly. Response to load current changes would be poor.

Next issue is the voltage sources are actually outputs from your regulators, which can only sink a few microamps. The reverse current through the 0.1 Ω sense resistor will only be about 32 μA, creating a voltage drop of ~3.2 μV. Depending on the offset voltage of each individual comparator, it may not turn the FET off at all (harmless in this case, but makes the 'ideal diode ' part of the circuit somewhat redundant).

Or if the offset voltage is positive it may turn off when the load current drops below a few milliamps, reducing output voltage by ~0.6 V (body diode voltage drop). This could be be good or bad depending on how much voltage the load needs for proper operation.

Dynamic stability of the circuit is unknown. Three current limiters operating in parallel with delays through the op amps and FETs may cause severe instability. Transient response of the regulators and load may exacerbate it.

Another possible problem is quiescent current draw. If you are wanting very low minimum current draw for the device then the consumption of this circuit is critical. The voltage dividers alone draw ~30 μA each, for a total of ~90 μA. The six op amps and required pull-down resistors could push minimum supply current up to well over 100 μA.

Bruce Abbott
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  • Missing the pulldown resistors is my bad, but easily resolved. When you say "can only sink a few microamps" do you have a reference where I can read some more? I've tried to find out what backfeeding an LDO does, which is why I've got the ideal diode at all. With a 2% output difference, I show one could have 3.366 and another 3.234, giving a .132 voltage differential and thus potential backflow over the 0.1 Ω of 1.32 amps, which would definitely get shut off by the comparator. If I add in some hysteresis I might be able to avoid a bad positive offset... would you review a revision? – Helpful Nov 19 '22 at 19:34
  • I didn't at all address the dynamic stability, which is what I was primarily thinking about when I asked this question. What techniques can I try to more accurately model that? As far as quiescent I have no problem changing resistor values, and I've found a few opamps with very low quiescent (500nA per amplifier). – Helpful Nov 19 '22 at 19:35
  • Backfeeding the LDO will turn it off. It will sink a tiny bit of current through the feedback voltage divider. If LDO output voltage exceeds input voltage by ~0.6V its internal FET body diode will conduct. This won't happen to you because all the regulators are supplied with the same voltage. – Bruce Abbott Nov 19 '22 at 23:50
  • To evualate stability you need to use real-world parts with accurate models, including the op amps, FETs, diodes, LDOs and load (especially its capacitance). Then switch the load on/off and see how your circuit responds to the disturbance. – Bruce Abbott Nov 20 '22 at 00:06
  • "Backfeeding the LDO will turn it off" - looking at the block diagram for my selected LDO, that makes plenty of sense but I was worried it might let out the magic smoke. if that's the case, I think I can simplify this and remove the reverse-protection entirely. I think that using a PMOS as - essentially - a controlled resistor to vary the output drop and roughly parallel them (actively) is a reasonable approach, but I'll need to simulate better to watch for oscillations. Thank you for the input! – Helpful Nov 20 '22 at 06:55
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Here is a simulation of a 3.3V LDO regulator using a PNP series element driven by an NPN transistor and low power rail-to-rail op-amp, that exhibits about 150 mV voltage drop at over 600 mA. The capacitors were necessary to eliminate oscillation which occurred mostly with input voltage below 3V. I also had to use lower values for the voltage divider and 1.25V regulator.

600 mA LDO regulator

I was also able to design an LDO using a series PMOS device. I had to add 100 mOhms in series to make it stable with a large (100 uF) load, which adds 60 mV drop at 600 mA. But it is not needed if the capacitor has a few hundred mOhms ESR, or if the resistive load is sufficient. So a 150 mV input-output differential can be achieved.

600 mA PMOS LDO regulator

Now I have designed a 3.3V 600mA LDO regulator using only commonly available 2N3904 and 2N3906 BJTs, and a PNP series device D45H11, and a 1.25V reference LT1004-1.2.

3.3V 600 mA Discrete LDO

PStechPaul
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  • It looks like essentially you've constructed an LDO out of discrete components, which is a really interesting approach. I like the simulation graph comparing different input voltages; have you simulated transients at all? – Helpful Nov 20 '22 at 06:48
  • The circuit is stable with a 100 uF capacitor on the output, and is OK with loads of 5 ohms and 500 ohms. It also works well with a D44H11 (which can handle 10A) and a QST3 which is good for 5A and has higher gain so the dropout voltage is only 54 mV. – PStechPaul Nov 20 '22 at 09:59