0

I'm designing a H-bridge driven by two IR2110 mosfet drivers and using four NMOS (IRFS SL7440) transistors. Below a picture of my schematic. I am using 98uF bootstrap capacitors, and apply two complementary 50 kHz pulses to the HIN and LIN inputs of the two mosfet drivers. This gives me a 50 kHz output block signal. Below are pictures of the HO1, LO1 outputs of the left mosfet driver. I can't seem to identify where the voltage spike at the rising edge of the HO block wave comes from. This results in a same voltage spike at the load v+ (the load is a 30 uH inductance). The NMOS transistors already have flyback diodes internally.

enter image description here

Could someone clarify what could be (a solution to) the issue? Because for my application I need a rather perfect output block signal before letting the coil make it sinusoidal.

toolic
  • 5,637
  • 5
  • 20
  • 33
Edward-__-
  • 1
  • 1
  • 2
    Doesn't 98 uF seem about 100 times too large? – Andy aka Nov 17 '22 at 18:03
  • How so? Do you have a good reference for choosing bootstrap capacitors? – Edward-__- Nov 17 '22 at 18:29
  • 1
    I have experience. – Andy aka Nov 17 '22 at 18:31
  • 1
    The bootstrap capacitor is clearly over valued and 98 µF can't work. Remember it is charged abruptly when the low-side switch conducts so think of the poor 4148 seeing all the current. Replace it by a 100-nF value and it should work better. In a real application, replace the 4148 by a MUR160 or equivalent. – Verbal Kint Nov 17 '22 at 18:31
  • 1
    Please [read this](https://electronics.stackexchange.com/questions/28251/rules-and-guidelines-for-drawing-good-schematics?r=Saves_AllUserSaves). – a concerned citizen Nov 17 '22 at 18:41

0 Answers0