I don't know what model you are using but, I am using the one found here (registration needed to avoid spammers). You'll need to make a minor adjustment: add 0 1k to the four arguments of I2 (something to do with a change in the way the PULSE() source now accepts arguments; not everyone agrees with it). You could update your OP with the contents of the .model (don't forget to add ``` at the beginning and at the end of the block of text).
At any rate, I recreated your schematic with the minor adjustment of having the resistor at the DRC pin after the current sense resistor (as seen in the datasheet, p. 13):
The main difference I see is that you have 15 V output, while I see 13.6 V. Maybe it's the model. C2 doesn't influence the output so its value isn't important. D2 might, though, that's why I've chosen one from the database (and added vp to its .model).
However, the ESR of the output capacitors does matter. I don't know what capacitor you've chosen, if it even is chosen from the database but, the lower the ESR the less influence its zero will have on the loop. For example, lowering it to 30m results in this current:
If you intended to "get a feeling" of how the circuit might work prior to building it by using this schematic, you're cheating yourself: never rely on defaults (D1), always add parasitics (Rser). If you want an even better feel then try to add more parasitics, including PCB (e.g. trace inductance, parasitic capacitances). But first, always test the model that it performs as it should. And, not lastly, always take a grain of salt, no matter the results -- not only SPICE is a simulator but, it does so through approximations, sometimes quite gross. For example, this model is behavioural, meaning it tries to model its behaviour, rather than its composition (transistor level), for the sake of speeding up. The price to pay may be deviations from the way the real chip performs.
[edit]
I meat to add this yesterday but forgot (it was too late): if you really need low ESR capacitor at the output then you can add the compensation as a capacitor placed in parallel with R3, like this:
If the ESR is in the single digits (e.g. 1 mΩ) or less then the value of C4 will need to be larger, to lower the zero and bring the phase to a suitable value. If the ESR is large enough then there is no need for C4 (the 1st picture). The difference is that you can get lower output ripple with C4.
