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I was trying to understand DDR, Trace-length, and signal integrity.

Most of the datasheets, For example, iMX8M Mini (Doc: IMX8MMHDG) clearly specifies what are the requirements for the each signal in the DDR interface.

enter image description here

However, if you see, for the clock (CK_t/CK_c) the maximum propagation delay allowed is 200ps. On PCB, wave propagates roughly at 6ps per 1mm velocity. So, for 200ps, maximum trace length will be 33mm.

iMX supports up to 1.5GHz clock, (3000MTS). And many PCs support almost same or slightly higher clock rate.

Here is my doubt, I have opened many mother boards to replace DIMM (dual in-line memory module) RAM. I often see that; those DIMM slots will be far away from CPU. How can they maintain signal integrity, even after placing CPU and DIMM slots so apart?

Aravind D. Chakravarti
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  • I think it may be because these are recommendations. Is there a section for absolute maximum? I think 33 mm may just be the point at which the signal is "electrically long", meaning that the rise time is seen across the entire length of the trace. Perhaps beyond 33 mm is totally okay but you will need to treat each conductor as a transmission line and ensure that there are no reflections. [This may be relevant](https://electronics.stackexchange.com/questions/175111/transmission-line-why-do-longer-traces-cause-signal-reflections) – Anas Malas Nov 11 '22 at 06:03
  • One reason for an absolute maximum propagation delay is that the CPU expects the new information to be there within a certain window. If the traces are too long, maybe it will read last cycle's data while new data is "en route" – Anas Malas Nov 11 '22 at 06:05
  • @AnasMalas Thanks. I get what you are saying. If length of trace is till "critical length", i.e., "electrically length" then there are less reflections. – Aravind D. Chakravarti Nov 11 '22 at 06:40

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