Bulk capacitance near a processor affecting converter transient response

Question

Here is my question: why do manufacturers of processors and FPGAs prescribe adding hundreds or thousands of microfarads of bulk capacitance next to their part?

The IGLOO2, for example, recommends a grand total of 1090uF of bulk cap on its core power rail. That is already a lot of cap, but it becomes a lot more when I add the recommended amount from my phy vendor and my processor vendor and my memory vendor, so on and so forth.

I often encounter two pieces of advice regarding bulk capacitance:

1. Bulk capacitance should be placed as close to your switching regulator as possible.
2. Bulk capacitance should be placed as close to your load as possible.

For this reason, I consider the topic of bulk capacitance to be qualitatively different than decoupling capacitance, where there is no such conflict of interest.

Liberally adding millifarads of cap all over the board is a valid resolution to this paradox, but it slows down my converter, which is capable of a 200kHz loop response, to 10 or 20 kHz.

Another resolution to the paradox is to greatly expand the number of converters in your system. One set of converters generates rails for the FPGA, another set for the processor, another set for the phys, and so on. I am aware of the effectiveness of the point-of-load solution. It is unfortunately not an option for most of what I work with.

The debate can be summed up another way. Is the ability to weather transients primarily a converter loop response problem, or is it a power integrity problem? How slow does a transient have to be before my converter is fast enough to reliably handle it?

It seems odd to me that, in the millifarad range, FPGA manufacturers would be making pronouncements on how much bulk cap you need. That seems like it would depend heavily on the rest of your system. Your regulators, other nearby loads, existing quantities of bulk cap, the geometry of your board, etc. How best am I to make sense of these claims?

Answer 1

There's no technical distinction with decoupling and bulk capacitance. It is all the same as far as physics goes. It's not a paradox but the fact that your decoupling vs bulk capacitance is a shorthand rule-of-thumb that makes assumptions which do not always apply.

It's just that high frequencies tend to contain less energy while low frequencies tend to contain more energy. Then there's the fact that large capacitances (required to decoupling high energies) tend to have high parasitic inductances (which low frequencies are less affected by) while low capacitances tend to have low parasitic inductances (which is required to decoupling high frequencies).

Therefore, decoupling of low frequencies tend to be capacitance limited while decoupling of high frequencies tend to be parasitic inductance limited. These two common scenarios mesh nicely with our available solutions

But these two are not the only cases. Four cases are possible between high/low energy and high/low frequency.

Low energy, low frequency is not interesting because the large capacitances with high parasitic inductance deal with that just fine. The low frequencies are less affected by the parasitic inductance and all things being equal, more capacitance leads to better decoupling.

But high energy, high frequency is a pickle, and that's what your FPGA has. FPGAs run at high frequency and can produce very large transient current demands. You need a lot of capacitance because your are decoupling high energy frequencies but you also need low parasitic inductance because these are high frequencies. Large capacitors have a parasitic inductance that is too high for the frequencies that need decoupling, but small capacitors have a capacitance that is too low for the energy that needs to be decoupled. So all you can do is use a lot of small capacitors with the appropriate ESL in parallel so that their cumulative capacitance is sufficient.