Why does this transistor shut off when another one is connected in parallel?

Question

I'm trying to build an XOR gate following this schematic without any simplifications:

Here is the circuit itself:

T1 and T4 are inverting the signal (the NOT gates), T2/T3 and T5/T6 are the AND gates, and the circuit is missing the final OR gate because I got lost at this point.

The resistors connected to the push buttons are 120 kΩ, the ones connected to the transistors are 5 kΩ and the ones connected to the LEDS are 180 Ω.

When I built the upper half alone it worked as expected, pushing B (right button) turns the LED on because the low A (left button) is then reversed to high and the AND outputs high.

The lower half worked as expected too, except it's the opposite, so pushing A (left button) turns the LED on.

But when both are connected at the same time, neither of the LEDs turn on under any circumstances. When I test with a multimeter, the bases of T3 and T6 are at around -0.8 V, and when buttons are pushed they are at around 1.5 V, but again, the LEDs are not turned on the slightest.

Here is a schematic to display the connections, I hope it's not confusing:

The input source is 5 V.

Answer 1

Your two-transistor AND gate and output indicators are wired like this:

^{simulate this circuit – Schematic created using CircuitLab}

This does not work because the LED will have current going through it if just B is a logic 1 regardless of what logic level A is at.

This thread on the EEVBlog:

https://www.eevblog.com/forum/projects/why-does-this-two-transistor-and-gate-not-work-as-expected/

suggests some alternatives such as:

and:

Answer 2

When you are talking about small numbers of BJTs and larger numbers of resistors in order to make logic gates, you are talking about RTL -- resistor-transistor logic. There is a design process involved. I provide a simplified example of that process for a 5 V RTL gate. Regardless, you don't just shoot from the hip if you plan to stack gates together, safely and securely.

Specifications are important. I've borrowed a diagram from that earlier post I mentioned (on the topic on a \$5\:\text{V}\$ RTL gate):

Above, you can see what's considered to be a valid LOW and HIGH and the area where an input voltage would be considered INVALID. Each stage can source a valid output HIGH for up to 6 specified sinking inputs, which is the more difficult, limiting case. (Each stage can easily sink a valid output LOW for many more inputs.)

I will use both RTL inverters and RTL NORs to construct the XOR. I will also add a standard LED driver switch. Since the maximum sourcing from a standard gate is about \$\frac{5\:\text{V}-2\:\text{V}}{4.7\:\text{k}\Omega}\ge 400\:\mu\text{A}\$, I set the LED current for \$6\:\text{mA}\$ (assumed saturated \$\beta=15\$.) It should work if you build it:

^{simulate this circuit – Schematic created using CircuitLab}

That's it. The way it works is to that \$Q_5\$ is a NOR gate, which takes as its inputs the outputs of two other NOR gates, \$Q_3\$ and \$Q_4\$. \$Q_3\$ just takes \$A\$ and \$B\$ as its inputs. But \$Q_4\$ takes \$\overline{A}\$ and \$\overline{B}\$ as its inputs. The circuit presents \$F=\overline{\overline{A+B} + \overline{\overline{A} + \overline{B}}}=\left(A+B\right)\cdot\left(\overline{A} + \overline{B}\right)=A\cdot\overline{B}+\overline{A}\cdot B\$. Which is an XOR.

I really hate the commonly found 'supposed' BJT AND gate that looks like this topology:

If you see one like that -- run, don't walk, away. It's nearly useless.

Answer 3

^{simulate this circuit – Schematic created using CircuitLab}

How would these work for logic gates? They should be expandable to multiple inputs.