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I have a TSX0102 level converter that is powered with local power. I'm running a UART through the TSX0102. The problem is I can't connect a serial to USB converter to the TSX0102 when the board is powered down because it pulls the input high and power bleeds through the TSX0102 inputs (and makes the VCC be somewhere between 0l.3 and 0.6V.)

How do I get a digital buffer to not bleees current through its inputs when the VCC is powered down?

schematic

simulate this circuit – Schematic created using CircuitLab

JRE
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Voltage Spike
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2 Answers2

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There is. For example 74LVC series chips. They allow e.g. 5V logic on input while powered down.

The TXS0102 is not very good choice. It has internal pull-ups. Even datasheet says TXB0102 could suit better for push-pull applications. Anyway, the TXS0102 data path should be high impedance if controlled with OE pin.

Unless specifically TXS or TXB buffer special features are required, there is a good chance simply using them for any random level translation application is likely to encounter problems, especially if long wires and incorrect external pull-ups/downs are involved.

TonyM
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Justme
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This is characteristic of, I think, 'VC' series families. So, LVC, VHC, etc. Certain bus interface families also have this property. You might choose VHC over LVC when the speed would be a liability, or when adequate headroom is desired for 5V operation (LVC is a bit dicey above 3.3V). Or CD4049 for higher voltages and even slower speeds, when Vin ≥ Vdd.

Tim Williams
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