What is the meaning of a negative capacitance in cadence virtuoso?
Here in the following image, I just want to find the capacitance of transistors using "print-->DC operating point". Can you please justify the negative value of capacitance? For example, why "cdg" capacitance is negative? As far as I know, we do not have negative capacitance.
These negative capacitances, as outputs of the BSIM model, simply suggest that the circuit's op-point/small-signal observable behavior (i.e. transistor terminal voltages and currents) is best described with a number of capacitor-like elements following \$I = C \frac{dV}{dt}\$, and some of the values of \$C\$ happened to end up being negative in the most numerically accurate description.
These negative capacitances aren't externally observable, and there are still positive capacitances (e.g. Cgg, Cbb, etc) present; the overall behavior of the transistor, when observed from the outside, should still be what you expect (the gate appears to have a positive capacitance, there is some Miller effect as if a positive parasitic \$C_{GD}\$ were present, etc), since the BSIM model does a pretty good job of modeling the transistor's observable circuit behaviors1.
This should not be surprising, as BSIM is not a physical model. It is an empirical model, whose goals first and foremost are to ensure that observables (voltages, currents, etc) are accurate. If you want physically accurate internal behaviors, consider using an EKV model if one is available from your silicon foundry.
1 BSIM does a good job, more observably accurate than EKV, for most scenarios. BSIM is claimed to have worse results than EKV for positive Vbs effects (I'm assuming the author of the article is referring to nFETs) and PTAT references at low temperature.
