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The 74185 is a binary-to-BCD converter. It is designed cleverly utilizing the fact that both 10 and 2^n are divisible by 2 once, thereby omitting processing of the LSB entirely. More interestingly even is that it can be cascaded to display arbitrary length digits.

The TI datasheet shows multiple configurations, for 6, 8, 9, 12, and 16 bit inputs. Though there clearly is a pattern of how to design those, it eludes me for the lower bit numbers. I cannot understand what is actually going on, understand why the circuit actually works and can be cascaded in the fashion shown in the datasheet. Can you explain how to come up with the cascade design and why it works?

Jonas Mechtheim
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  • Before I bother writing about it (and I have already done so here), have you ***read*** [the description](https://i.stack.imgur.com/OthJQ.png) found in the Texas Instruments databook on the 7400 series parts and attempted to understand it, on paper? There is also, on Wikipedia, this link to the related [double dabble](https://en.wikipedia.org/wiki/Double_dabble) concept. From these, you should be able to get pretty close. – jonk Oct 29 '22 at 21:51
  • You can see where I show the logic (which TI doesn't do for the 74185 as it is read-only memory-based) for a 4-in, 4-out section [here](https://electronics.stackexchange.com/a/441405/38098) along with some discussion. And [here](https://electronics.stackexchange.com/a/499916/38098) is some expansion on the idea. (The table in the latter answer can be expanded to 5-in, 5-out -- the 74185 doesn't use Y6 or Y7.) Let me know what remains to be understood that isn't dealt with elsewhere or is dealt with but not in a way you can follow. – jonk Oct 29 '22 at 22:03
  • Oh. My mistake. I meant that the 74185 doesn't use Y7 or Y8. And you will need a table of 5-in and 6 out. But otherwise, it follows all the logic I mentioned. I just need to read what I'm writing before I post it. ;) – jonk Oct 29 '22 at 23:30

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