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I am making a circuit that creates various subdivisions of input frequency by integer values from f/2 down to f/12. Division by 2, 4, 8 are straightforward using JK flip flops. Divisions by 6, 9, 12 can be done via combining divisions by 2 and 3 in sequences. The most tricky are 5, 7, 11.

CD4018 seems to fit the purpose for this task. It's datasheet provides examples of division by 5 and 7 with additional CD4011 on page 5.

As for division by 11 - according to the datasheet it's possible to use multiple CD4018 to divide by numbers larger than 10. The following appnote provides a circuit for programmable multidecade divider: enter image description here

I suppose it should be possible to simplify this schematic to the required divide-by-11 but reading its description I am not exactly sure how it works. It seems that "hundreds" can be omitted and J1-J5 on the remaining CD4018s set either to 0 or 1 to provide required value. However I am not sure what to do with additional logic ICs mentioned on the schematic.

I would appreciate if someone could explain how I can accomplish division by 11 using CD4018.

Ivan Demyachenko
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    Wouldn't it be easier to use a 4-bit binary counter than the 4018? Why must the solution use the 4018? – Elliot Alderson Oct 29 '22 at 14:49
  • @ElliotAlderson could you please elaborate on how to use 4-bit binary counter to divide by 11? 4018 doesn't have to be the solution - I just have several of these chips and found the mentioned schematic - I thought it might be easier using 4018. – Ivan Demyachenko Oct 29 '22 at 14:58
  • This [RCA appnote](https://www.one-electron.com/Archives/RCA/RCA-AppNotes/RCA%201970%20ICAN-6498%20Using%20the%20CD4018%20Divide-by-N%20Counter.pdf) has a better explanation of how to use the multiple CD4018 configuration. – ErikR Oct 29 '22 at 15:18
  • Here's an explanation of how to use counters with presets to obtain division: http://www.wenzel.com/wp-content/uploads/161divdr.pdf For divide-by-11 you'll only need one '161 with TC connected back to /LOAD through an inverter. Are you looking for 50% duty cycle on the output? – ErikR Oct 29 '22 at 15:40
  • @ErikR thank you for the link! Yes, I am looking for 50% duty cycle. Does this schematic output less than 50%? – Ivan Demyachenko Oct 29 '22 at 17:52
  • Does the input signal have 50% duty cycle? – Bruce Abbott Oct 29 '22 at 19:35
  • @BruceAbbott yes – Ivan Demyachenko Oct 29 '22 at 19:40
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    The 4018 doesn't give 50% duty cycle for odd divisors. If you look at Fig. 4c on page 3 of the RCA app note you'll see that for divide by 7 the outputs are HIGH for 4 clocks and LOW for 3 clocks. – ErikR Oct 29 '22 at 23:47

2 Answers2

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This approach doesn't use the 4018, but it does demonstrate a technique you can use to generate a divide by N counter with 50% duty cycle. The steps to this approach are:

  1. Generate a modulo 11 counter.
  2. Construct a waveform that has 5 ones followed by 6 zeros.
  3. Extend the run of ones by 1/2 clock using an additional flip-flop and OR gate.

Here is a solution using a 74161 shown in Logisim:

enter image description here

The 74161 is set up to count starting from 5 which creates the modulo 11 counter.

The AND/OR/AND gates create a stream of 5 ones and 6 zeros.

The flip-flop and OR gate is a technique to extend a string of ones by one half clock cycle.

Here is the timing diagram:

enter image description here

You can see that Qout is high for exactly 11 half-cycles.

ErikR
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  • Thank you for the detailed example! Perhaps it would be possible to use flip-flop and OR gate technique to equalize CD4018 cycles. Could you please point me to some literature where this technique is described in detail? – Ivan Demyachenko Oct 30 '22 at 07:53
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Sharing another solution that I found in case anyone else would be interested: according to the accepted answer in this question division by odd integers can be done using flip-flops and XOR gates. Stacking divide-by-3 & divide-by-4 & XOR gate can produce desired divide-by-11 circuit: enter image description here enter image description here

Fout half cycle seems to be 11 Fin half cycles and duty cycle is 50%. However the first half cycle of Fout is only 10 half cycles of Fin. Although this is irrelevant for my purpose - in case anyone can explain this behavior I would be grateful.

Ivan Demyachenko
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