My test bench in VHDL is always showing U for all values

Question

I am learning VHDL for a University course.

My code:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 entity operations is 
 Port (x : in STD_LOGIC_VECTOR ( 2 downto 0) ;s : in STD_LOGIC_VECTOR (1 downto 0) ;
 F : out STD_LOGIC_VECTOR (5 downto 0));
 end operations;
 
 architecture dataflow of operations is 
 
 begin
F(5)<= x(2)and x(1) and s(1) and (not s(0));
 
F(4)<= (x(2) and (not x(1)) and x(0) and (not s(0))) or (x(2) and x(0)and s(1) and (not s(0))) or ( x(2)and x(1) and s(1) and s(0));

F(3)<= (x(2) and (not x(1)) and x(0) and s(1)) or (x(2) and x(0)and s(1) and s(0)) or ((not x(2)) and x(1) and x(0) and s(1) and (not s(0)));

F(2)<= (x(2) and (not x(1)) and s(0)) or (x(2) and(not s(1)) and (not s(0))) or ((not x(2)) and x(1) and x(0) and s(0));

F(1)<= (x(2) and(not s(1)) and (not s(0))) or (x(1) and x(0)and (not s(1)) and ( not s(0))) or
((not x(2)) and (not x(1)) and x(0) and(not s(1)) and s(0)) or ((not x(2)) and x(1) and (not x(0)) and s(0)) 
or (x(1) and (not x(1)) and (not s(1)) and s(0)) ;

F(0)<= (x(2) and(not s(1)) and (not s(0))) or ((not X(0))and s(1) ) or (x(1) and (not s(0)) and (not x(0))) 
or ((not x(2)) and (not x(1)) and x(0) and s(0));
 
 end dataflow;

Test bench:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity testbench is
--  Port ( );
end testbench;

architecture Behavioral of testbench is

component operations
Port (x : in STD_LOGIC_VECTOR ( 2 downto 0) ;s : in STD_LOGIC_VECTOR (1 downto 0) ;
 F : out STD_LOGIC_VECTOR (5 downto 0));
 end component;
 --INPUTS
signal x: std_logic_vector ( 2 downto 0); 
signal s: std_logic_vector ( 1 downto 0);

signal F: std_logic_vector(5 downto 0);

begin

uut: operations port map(x=>x,s=>s,F=>F);
Stim_proc: process
begin 
      x<= "001";s<="00"; wait for 100ns;


end process;
END;

The x, s, and F values are U constantly.

Is the waveform diagram looking at the signals in the testbench level or on the dut level? I also noticed that you put the architecture of "operation" to "dataflow" while the test bench is "behavioral". These usually need to match. — pknodle, Oct 24 '22 at 20:23
testbench level and even when i try using another component implemented using behavioral it gives the same output — Nour Samir, Oct 24 '22 at 21:03

score 1 · Accepted Answer · answered Oct 24 '22 at 21:17

Make sure you zoom the wave form:

Looks fine here (also using Vivado). Adding a wait at the end of the process blocks the simulation. You should also avoid the 2 non-standard libraries.

library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is
end testbench;

architecture Behavioral of testbench is

component operations
Port (x : in STD_LOGIC_VECTOR(2 downto 0);
      s : in STD_LOGIC_VECTOR(1 downto 0);
      F : out STD_LOGIC_VECTOR(5 downto 0));
end component;

signal x: std_logic_vector(2 downto 0); 
signal s: std_logic_vector(1 downto 0);
signal F: std_logic_vector(5 downto 0);

begin
    uut: operations port map(x=>x,s=>s,F=>F);
    Stim_proc: process
    begin 
        x<= "001";s<="00"; wait for 100ns;
        x<= "001";s<="01"; wait for 100ns;
        x<= "000";s<="01"; wait for 100ns;
        x<= "000";s<="00"; wait for 100ns;
        wait;
    end process;
END;

My test bench in VHDL is always showing U for all values

1 Answers1